EPM5032DC-20 vs EPM5032DC-25 比較

詳細な並列比較: EPM5032DC-20 メーカー: Intel および EPM5032DC-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5032DC-20 EPM5032DC-25
ブランド Intel Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete NRND
在庫状況 In Stock In Stock
単価(USD) $5.05 $3.55
Product Family MAX 5000 MAX 5000
Device Type CPLD (Complex Programmable Logic Device) UV Erasable Programmable Logic Device (EPLD)
Programmable Technology UV-Erasable / OTP EPROM —
Usable Gates 600 —
Macrocells 32 32
Maximum Frequency (fCNT) 71.4 MHz —
Pin-to-Pin Delay (tPD) 20 ns —
Speed Grade -20 —
Supply Voltage (VCC) 5 V —
パッケージ 20-pin DIP (Windowed Ceramic, 0.3" wide) CDIP-28 (Windowed Ceramic DIP-28)
実装タイプ Through-Hole —
Logic Blocks 4 Logic Array Blocks (LABs) —
I/O Pins [DATA_NEEDED: I/O pin count for DIP-20 variant] —
動作温度 [DATA_NEEDED: commercial/industrial/military grade] [DATA_NEEDED: operating temperature range]
RoHS ステータス Compliant (per IC-Components listing) Lead Free / RoHS Compliant (per distributor listings)
Lead Free [DATA_NEEDED: confirmed lead-free] —
Manufacturer Altera (now Intel Programmable Solutions Group) Altera (Intel Programmable Solutions Group)
Programming Method Altera MAX+PLUS II / Quartus (legacy support) UV erase + Altera/Intel MAX+PLUS II programmer
Pin-to-Pin Propagation Delay (tPD) — 25 ns
Maximum Counter Frequency (fCNT) — [DATA_NEEDED: maximum counter frequency]
Setup Time (tSU) — [DATA_NEEDED: setup time]
Number of Dedicated Inputs — 32 (in DIP-28 pinout)
Number of I/O Pins — 22 (in DIP-28 pinout, 4 used as dedicated inputs)
Process Technology — CMOS, EPROM (UV-Erasable)
Architecture — PAL-Type, Single-LAB, 32-Macrocell
Output Structure — Programmable I/O with output enable
Flip-Flop Configuration — D, T, JK, or SR (programmable)
Erasure Method — UV light through ceramic window

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