EPM5032DC-20 vs EPM5032DC-25 비교

다음의 상세 나란히 비교: EPM5032DC-20 제조: Intel 및 EPM5032DC-25 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5032DC-20 EPM5032DC-25
브랜드 Intel Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete NRND
재고 상태 In Stock In Stock
단가 (USD) $5.05 $3.55
Product Family MAX 5000 MAX 5000
Device Type CPLD (Complex Programmable Logic Device) UV Erasable Programmable Logic Device (EPLD)
Programmable Technology UV-Erasable / OTP EPROM —
Usable Gates 600 —
Macrocells 32 32
Maximum Frequency (fCNT) 71.4 MHz —
Pin-to-Pin Delay (tPD) 20 ns —
Speed Grade -20 —
Supply Voltage (VCC) 5 V —
패키지 20-pin DIP (Windowed Ceramic, 0.3" wide) CDIP-28 (Windowed Ceramic DIP-28)
실장 유형 Through-Hole —
Logic Blocks 4 Logic Array Blocks (LABs) —
I/O Pins [DATA_NEEDED: I/O pin count for DIP-20 variant] —
동작 온도 [DATA_NEEDED: commercial/industrial/military grade] [DATA_NEEDED: operating temperature range]
RoHS 상태 Compliant (per IC-Components listing) Lead Free / RoHS Compliant (per distributor listings)
Lead Free [DATA_NEEDED: confirmed lead-free] —
Manufacturer Altera (now Intel Programmable Solutions Group) Altera (Intel Programmable Solutions Group)
Programming Method Altera MAX+PLUS II / Quartus (legacy support) UV erase + Altera/Intel MAX+PLUS II programmer
Pin-to-Pin Propagation Delay (tPD) — 25 ns
Maximum Counter Frequency (fCNT) — [DATA_NEEDED: maximum counter frequency]
Setup Time (tSU) — [DATA_NEEDED: setup time]
Number of Dedicated Inputs — 32 (in DIP-28 pinout)
Number of I/O Pins — 22 (in DIP-28 pinout, 4 used as dedicated inputs)
Process Technology — CMOS, EPROM (UV-Erasable)
Architecture — PAL-Type, Single-LAB, 32-Macrocell
Output Structure — Programmable I/O with output enable
Flip-Flop Configuration — D, T, JK, or SR (programmable)
Erasure Method — UV light through ceramic window

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