EPM5032DI-25 vs EPM5016DC-20 比較
詳細な並列比較: EPM5032DI-25 メーカー: Altera および EPM5016DC-20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5032DI-25 | EPM5016DC-20 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $18.20 | $16.50 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable Programmable Logic Device (PLD) | EPLD (UV-Erasable Programmable Logic Device) |
| Architecture | PAL-type, CMOS, AND-OR sum-of-products | PAL-type macrocell with Programmable Interconnect Array (PIA) |
| Macrocells | 32 | 16 |
| Product Terms | 320 | 160 |
| Logic Gates | [DATA_NEEDED: equivalent gate count] | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | — |
| Total Array Inputs | 24 | — |
| Registered Outputs | 16 | — |
| Global Clocks | 1 | — |
| Propagation Delay (tPD) | 25 ns | 20 ns |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| 電源電圧 | 5 V | — |
| Process Technology | CMOS | CMOS, UV-erasable |
| パッケージ | Ceramic DIP, windowed (UV-erasable) | — |
| ピン数 | [DATA_NEEDED: exact pin count - 24 or 28] | — |
| 動作温度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| I/O Standard | TTL-compatible | — |
| Programmability | UV-erasable, EPROM-based | — |
| Development Tool | MAX+PLUS II / A+PLUS | — |
| RoHS ステータス | [DATA_NEEDED: likely non-compliant due to ceramic DIP] | [DATA_NEEDED: RoHS compliance] |
| Lifecycle | Not Recommended for New Designs (NRND) | — |
| I/O Pins | — | 8 |
| 最大クロック周波数 | — | 62.5 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Nominal Supply Voltage | — | 5.0 V |
| Package Type | — | 20-pin Ceramic DIP (Cerdip) with UV window |
| Package Suffix Code | — | DC = Ceramic DIP, Commercial |
| Speed Grade | — | -20 = 20 ns tPD |
| Programming Method | — | UV erase + EPROM-style programming via Altera programming hardware |