EPM5032PC-20 vs EPM5032PC-15 比較
詳細な並列比較: EPM5032PC-20 メーカー: Altera および EPM5032PC-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5032PC-20 | EPM5032PC-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.05 | $8.10 |
| Device Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable PLD) |
| Programming Type | OTP (One-Time Programmable) | — |
| Macrocells | 32 | — |
| Usable Gates | 600 | 600 |
| Logic Blocks | 2 Logic Array Blocks | — |
| Product Terms | 320 | — |
| Dedicated Inputs | 24 | 7 |
| Bidirectional I/O Lines | 16 | — |
| Propagation Delay (tPD) | 20 ns | 15 ns |
| 最大クロック周波数 | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Technology | CMOS, 0.65 um process | — |
| Architecture | PAL-type macrocells with Programmable Interconnect Array (PIA) | — |
| パッケージ | PDIP-28 (Plastic DIP, 28-pin) | 28-pin PDIP (PC suffix = windowed CerDIP) |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| 実装タイプ | Through-Hole | Through-Hole (DIP) |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Non-compliant (CerDIP window, contains Be) |
| Macro Cells | — | 32 |
| Logic Elements / LABs | — | 1 LAB (4 macrocells per group) |
| Maximum Internal Frequency | — | 76.9 MHz (some sources list 83.3 MHz) |
| Operating Voltage (VCC) | — | 5 V (typ.) |
| Technology Node | — | 0.8 micron CMOS |
| Configuration Memory | — | UV-Erasable EPROM |
| Bidirectional I/O Pins | — | 16 |
| Total Array Inputs | — | 24 |
| Pin/Package Suffix | — | PC = Windowed Ceramic DIP |
| Speed Grade | — | 15 (15 ns tPD) |
| Programming Tool | — | Altera Logic Programmer + MAX+plus II |
| Lead-Free | — | No |