EPM5064JC vs EPM5032JC-20 比較
詳細な並列比較: EPM5064JC メーカー: Altera および EPM5032JC-20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5064JC | EPM5032JC-20 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.10 | $9.75 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | — |
| Macrocells | 64 | 32 |
| Usable Gates | 1,250 (approx.) | — |
| Logic Array Inputs | 36 | — |
| Logic Array Outputs | 64 | — |
| パッケージ | 68-pin PLCC (JEDEC) | 68-pin JLCC (windowed ceramic) |
| 実装タイプ | Surface Mount (socketed) | — |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | — |
| I/O Logic Level | TTL / CMOS compatible | — |
| Configuration Memory | EPROM (UV-erasable window or OTP) | — |
| 動作温度 | [DATA_NEEDED: operating temperature grade] | — |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | — |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | — | 1 |
| Product Terms (P-terms) | — | 320 |
| Propagation Delay (tPD) | — | 20 ns |
| 最大クロック周波数 | — | 62.5 MHz |
| Setup Time | — | 10 ns |
| I/O Lines | — | 16 (bidirectional) |
| Dedicated Inputs | — | 8 |
| Total Inputs | — | 24 |
| Process Technology | — | CMOS |
| Erase Method | — | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | — | 12 V |
| Architecture | — | PAL-type AND-OR array with PIA interconnect |
| ライフサイクル状態 | — | Obsolete (legacy Altera MAX 5000) |