EPM5064JI-1 vs EPM5064LC-2 比較
詳細な並列比較: EPM5064JI-1 メーカー: Intel および EPM5064LC-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5064JI-1 | EPM5064LC-2 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $3.40 | $8.40 |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 64 | 64 |
| User I/O Pins | [DATA_NEEDED: user I/O count from datasheet] | — |
| パッケージ | 68-pin PLCC (windowed ceramic) | PLCC-44 (J-Lead, plastic) |
| Logic Elements | [DATA_NEEDED: total logic elements] | — |
| Propagation Delay (tPD) | [DATA_NEEDED: combinational tPD from datasheet] | 45 ns |
| 電源電圧 | 5 V | — |
| 動作温度 | [DATA_NEEDED: commercial vs industrial grade temp range] | -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] |
| Process Technology | CMOS, UV-erasable | CMOS, OTP EPROM (UV-erasable base) |
| Speed Grade | JI-1 (commercial, -10/-12/-15 family) | — |
| Programmability | UV-erasable (windowed package) | — |
| Data Retention | 25 years (per MAX 5000 datasheet) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: not stated in provided data] | [DATA_NEEDED: not specified in source] |
| Device Family | — | MAX 5000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 4 |
| Logic Elements per LAB | — | 16 |
| Number of Inputs | — | 36 (7 dedicated + 28 I/O) |
| Number of I/O Pins | — | 28 |
| Number of Flip-Flops | — | 28 |
| Maximum Internal Frequency | — | 40 MHz |
| Programmable Polarity | — | Yes |
| Programmable Output Enable | — | Yes, per macrocell |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programming Method | — | Altera byte-wide / JTAG programmer |