EPM5128GC-1 vs EPM5128GC2 比較
詳細な並列比較: EPM5128GC-1 メーカー: Altera および EPM5128GC2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5128GC-1 | EPM5128GC2 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $18.95 | $54.00 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable CMOS CPLD | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | 2.5K |
| Dedicated Inputs | 7 | 16 |
| Maximum User I/O Pins | 52 | — |
| Nominal Supply Voltage | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 16 ns (typical, -1 speed grade) | — |
| パッケージ | PGA-96+ (Pin Grid Array, ceramic windowed) | Ceramic PGA (GC, windowed) |
| Technology | CMOS, UV-erasable EPROM | — |
| 動作温度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| IOL / IOH | 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) | — |
| Security Bit | Programmable, prevents readback | — |
| Programming Method | UV erase + EPROM program (or device programmer) | — |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 (16 macro cells each) |
| Maximum Internal Frequency | — | 50 MHz |
| Supply Voltage VCC | — | 5 V |
| I/O Pins | — | 64 |
| Programmable Flip-Flop Modes | — | D / T / JK / SR (selectable) |
| Architecture | — | AND/OR plane + programmable macro cell + PIA |
| Process Technology | — | CMOS EPROM |
| Reprogrammability | — | UV-erasable (windowed ceramic package) |
| Configuration Memory | — | On-chip EPROM (no external boot device) |
| ピン数 | — | [DATA_NEEDED: total PGA pin count] |