EPM5128JC vs EPM5128GC-1 比較
詳細な並列比較: EPM5128JC メーカー: Altera および EPM5128GC-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5128JC | EPM5128GC-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.75 | $18.95 |
| Product Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | UV-erasable CMOS CPLD |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 35 ns | 16 ns (typical, -1 speed grade) |
| Logic Elements | Programmable AND/OR/XOR array | — |
| Supply Voltage (VCC) | 5 V (typical) | — |
| ピン数 | 68 | — |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | — |
| Dedicated Inputs | 8 | 7 |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Configuration Memory | UV-erasable EPROM (windowed package) | — |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | — |
| 動作温度 | Commercial 0C to +70C | -40C to +85C (industrial) |
| 実装タイプ | Surface Mount (PLCC socket or solder) | — |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | — |
| Process Technology | CMOS EPROM | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status - legacy part] | [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 |
| Macrocells | — | 128 |
| Usable Gates | — | 2,500 |
| Maximum User I/O Pins | — | 52 |
| Nominal Supply Voltage | — | 5 V |
| Supply Voltage Range | — | 4.75 V to 5.25 V |
| Maximum Operating Frequency | — | 62.5 MHz |
| パッケージ | — | PGA-96+ (Pin Grid Array, ceramic windowed) |
| Technology | — | CMOS, UV-erasable EPROM |
| IOL / IOH | — | 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) |
| Security Bit | — | Programmable, prevents readback |
| Programming Method | — | UV erase + EPROM program (or device programmer) |
| MSLレベル | — | [DATA_NEEDED: MSL level] |