EPM5128JC vs EPM5128GC-1 Comparação

Comparação detalhada lado a lado de EPM5128JC por Altera e EPM5128GC-1 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EPM5128JC EPM5128GC-1
Marca Altera Altera
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Obsolete Obsolete
Status do estoque In Stock In Stock
Preço unitário (USD) $9,75 $18,95
Product Family MAX 5000 —
Device Type EPLD / CPLD UV-erasable CMOS CPLD
Macrocell Count 128 —
Propagation Delay (tPD) 35 ns 16 ns (typical, -1 speed grade)
Logic Elements Programmable AND/OR/XOR array —
Supply Voltage (VCC) 5 V (typical) —
Número de pinos 68 —
Package Type PLCC-68 (JLCC) ceramic, J-leaded —
Dedicated Inputs 8 7
User I/O Pins [DATA_NEEDED: user I/O pin count] —
Configuration Memory UV-erasable EPROM (windowed package) —
Programming Interface Altera MAX+PLUS II / A+PLUS / legacy programmer —
Temperatura de operação Commercial 0C to +70C -40C to +85C (industrial)
Tipo de montagem Surface Mount (PLCC socket or solder) —
Boundary Scan JTAG IEEE 1149.1 (family feature) —
Process Technology CMOS EPROM —
Status RoHS [DATA_NEEDED: RoHS status - legacy part] [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy]
Lead-Free [DATA_NEEDED: lead-free status] —
Family — MAX 5000
Macrocells — 128
Usable Gates — 2,500
Maximum User I/O Pins — 52
Nominal Supply Voltage — 5 V
Supply Voltage Range — 4.75 V to 5.25 V
Maximum Operating Frequency — 62.5 MHz
Encapsulamento — PGA-96+ (Pin Grid Array, ceramic windowed)
Technology — CMOS, UV-erasable EPROM
IOL / IOH — 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec])
Security Bit — Programmable, prevents readback
Programming Method — UV erase + EPROM program (or device programmer)
Nível MSL — [DATA_NEEDED: MSL level]

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