EPM5128LC-1 vs EPM5128JC-1 比較
詳細な並列比較: EPM5128LC-1 メーカー: Altera および EPM5128JC-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5128LC-1 | EPM5128JC-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.20 | $24.95 |
| Family | MAX 5000 | MAX 5000 |
| Logic Elements / Macrocells | 128 macrocells | — |
| Number of Usable Gates | [DATA_NEEDED: usable gates] | — |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 52 | — |
| Total User I/O | 60 (max) | — |
| Propagation Delay (tpd) | 30 ns | — |
| Supply Voltage (VCC) | 5 V (±10%) | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | CMOS EPROM, UV-erasable | — |
| Programmability | UV-erasable / OTP (windowed package) | — |
| Package Type | 68-pin J-lead ceramic chip carrier (PLCC windowed) | — |
| 動作温度 | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade] |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| 実装タイプ | Surface Mount (J-lead PLCC socket compatible) | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | non_compliant (ceramic windowed package) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | Erasable Programmable Logic Device (EPLD/CPLD) |
| Macrocells | — | 128 |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Maximum Operating Frequency | — | 62.5 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 40 ns |
| Technology | — | CMOS, UV-erasable EPROM |
| パッケージ | — | 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) |
| Programming Interface | — | JTAG / Altera dedicated programmer |
| Configuration Memory | — | Non-volatile EPROM (UV-erasable) |
| ライフサイクル状態 | — | Obsolete - last-time-buy inventory only |