EPM5130LC vs EPM5130WC-1 比較
詳細な並列比較: EPM5130LC メーカー: Altera および EPM5130WC-1 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EPM5130WC-1 - 128-Macrocell 40ns UV CPLD, 100-pin CQFP | Intel (Altera) MAX 5000
EPM5130WC-1 Obsolete仕様比較
| パラメータ | EPM5130LC | EPM5130WC-1 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $15.60 | $85.00 |
| Series | MAX 5000 | MAX 5000 |
| Family | MAX 5000 (EPM51xx) | — |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| User I/O Pins | 48 | Up to 100 |
| Total Inputs (Dedicated + I/O) | 68 | — |
| Dedicated Inputs | 19 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Maximum Internal Clock Frequency | 50 MHz | — |
| Global Clock Inputs | 1 | — |
| Configuration Technology | UV-Erasable / OTP EPROM | — |
| Process Technology | CMOS (0.7 um EPROM) | CMOS EPROM |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| I/O Standard | TTL-compatible | — |
| パッケージ | JLCC-68 (J-Lead Ceramic Chip Carrier) | — |
| 動作温度 | [DATA_NEEDED: commercial/industrial/military grade] | [DATA_NEEDED: operating temperature range] |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS compliance] |
| Manufacturer | — | Altera (now Intel) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocell Count | — | 128 |
| Logic Array Blocks | — | Multiple LABs (per MAX 5000 architecture) |
| Propagation Delay (tpd) | — | 40 ns |
| 最大クロック周波数 | — | 50 MHz |
| Erasure Method | — | UV (ultraviolet, windowed package) |
| Package Type | — | 100-pin Ceramic QFP (Windowed) |
| 電源電圧 | — | [DATA_NEEDED: VCC nominal] |
| Programmable | — | Yes (UV-erasable, non-volatile) |
| Logic Family | — | MAX 5000 (Altera) |
| Configuration Memory | — | EPROM (on-chip) |