EPM5130WC-2 vs EPM5130WC-1AA 比較
詳細な並列比較: EPM5130WC-2 メーカー: Altera および EPM5130WC-1AA メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5130WC-2 | EPM5130WC-1AA |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $62.00 | $54.25 |
| Device Family | MAX 5000 | MAX 5000 |
| Product Type | UV-Erasable PLD (CPLD) | — |
| Macrocell Count | 128 | 128 |
| Propagation Delay (tPD) | 45 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V nominal |
| 動作温度 | 0 °C to 70 °C (Commercial) | [DATA_NEEDED: commercial or industrial temp grade] |
| Process Technology | CMOS | 5 V CMOS, UV-erasable |
| Dedicated Inputs | 19 | 19 |
| User I/O Lines | 48 | — |
| Total Inputs (I/O + dedicated) | 68 | — |
| Package Type | 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing | — |
| Terminal Pitch | 0.650 mm | — |
| 実装タイプ | Surface Mount | — |
| Configuration Memory | UV-erasable CMOS EEPROM cells | — |
| Speed Grade | -2 (45 ns) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | unknown (legacy package, likely non-compliant) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | AND/OR array with programmable macrocell register | — |
| Number of Logic Array Blocks | — | 8 (typical for MAX 5130) |
| Propagation Delay (tPD, max) | — | 40 ns |
| Maximum Toggle Frequency (fCNT) | — | 50 MHz |
| Maximum Clock Frequency (fMAX) | — | [DATA_NEEDED: fMAX exact value] |
| I/O Pins | — | 48 |
| Total Inputs (incl. I/O feedback) | — | 68 |
| Total Outputs | — | 48 |
| パッケージ | — | Windowed Ceramic WQFP (AA suffix) |
| Programming Method | — | UV erase + EPROM programming |
| Logic-to-Pin Ratio | — | Highest in-class per Altera marketing literature |