EPM5192AGC-15 vs EPM5192AJI84-15 比較
詳細な並列比較: EPM5192AGC-15 メーカー: Altera および EPM5192AJI84-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192AGC-15 | EPM5192AJI84-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $27.80 | $27.80 |
| Product Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable / OTP Complex PLD |
| Series | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (typical for 192-macrocell MAX 5000) | — |
| Maximum User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | 15 ns |
| Supply Voltage (VCC) | 5 V | 4.5 V to 5.5 V (nominal 5 V) |
| Technology | CMOS, UV-erasable EPROM | — |
| パッケージ | Ceramic Pin Grid Array (PGA) | — |
| Programming Method | UV erase + EPROM program (via Altera programmer) | UV erase + EPROM program via standard Altera programmer |
| 動作温度 | [DATA_NEEDED: operating temperature range] | -40 °C to +85 °C (Industrial, 'I' suffix) |
| RoHS ステータス | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] | unknown |
| ライフサイクル状態 | Obsolete / Last Time Buy (per Altera legacy product list) | — |
| Device Family | — | MAX 5000 EPLD |
| Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins | — | 84 |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Package Type | — | 84-pin JLCC (J-Leaded Ceramic Chip Carrier) with quartz window |
| 実装タイプ | — | Through-Hole (SMD socket-compatible) |
| Design Tool Support | — | MAX+PLUS II (legacy); not supported by modern Quartus Prime |
| Lead-Free | — | unknown |
| ハロゲンフリー | — | unknown |
| Functional Equivalent (Plastic OTP) | — | EPM5192AJC84-15 (windowless plastic JLCC, same die) |