EPM5192AGC84-20 vs EPM51929C 比較
詳細な並列比較: EPM5192AGC84-20 メーカー: Altera および EPM51929C メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192AGC84-20 | EPM51929C |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $41.20 | $9.40 |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 5000 | — |
| Macrocells | 192 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Logic Gates (typical) | [DATA_NEEDED: typical gate count] | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | — |
| パッケージ | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) | — |
| Package Code | WPGA | — |
| Erasure Method | UV-Erasable (with OTP window) | — |
| Process Technology | CMOS | — |
| Operating Temperature Grade | Commercial | — |
| 電源電圧 | [DATA_NEEDED: VCC range] | [DATA_NEEDED: VCC range] |
| I/O Standard | 5V CMOS / TTL compatible | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | unknown |
| 実装タイプ | Through-Hole (Pin Grid Array socket) | Surface Mount or Through-Hole (package dependent) |
| Device Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Architecture | — | Multi-array matrix (PAL-based macrocells) |
| Logic Density | — | [DATA_NEEDED: usable gates] |
| Number of Macrocells | — | [DATA_NEEDED: macrocell count] |
| ピン数 | — | [DATA_NEEDED: pin count] |
| Package Type | — | [DATA_NEEDED: package suffix - C denotes commercial temperature grade] |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-erasable, JEDEC fuse map |
| 動作温度 | — | Commercial (0C to +70C) |
| Propagation Delay | — | [DATA_NEEDED: tpd specification] |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fmax] |
| Lead-Free | — | unknown |
| MSLレベル | — | [DATA_NEEDED] |