EPM5192AQC-2 vs EPM5192AGC-15 比較
詳細な並列比較: EPM5192AQC-2 メーカー: Altera および EPM5192AGC-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192AQC-2 | EPM5192AGC-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.50 | $27.80 |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | — |
| Series | MAX 5000 (EPM5192) | MAX 5000 |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | 72 |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | 15 ns (pin-to-pin, -15 speed grade) |
| 最大クロック周波数 | [DATA_NEEDED: max fMAX for -2 grade] | — |
| Process Technology | CMOS | — |
| Switch Matrix | UV-Erasable / OTP (windowless on AQC package) | — |
| パッケージ | 100-pin PQFP (R-PQFP-G100) | Ceramic Pin Grid Array (PGA) |
| Lead Pitch | 0.635 mm | — |
| Terminal Form | Gull-wing | — |
| 動作温度 | [DATA_NEEDED: commercial / industrial / military grade] | [DATA_NEEDED: operating temperature range] |
| 実装タイプ | Surface Mount | — |
| Programming Interface | JTAG (IEEE 1149.1) boundary scan | — |
| RoHS ステータス | [DATA_NEEDED: confirmed compliance status] | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Array Blocks | — | 16 (typical for 192-macrocell MAX 5000) |
| Maximum User I/O Pins | — | 64 |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Method | — | UV erase + EPROM program (via Altera programmer) |
| ライフサイクル状態 | — | Obsolete / Last Time Buy (per Altera legacy product list) |