EPM5192AQM100-20 vs EPM5192AQM100-15 比較
詳細な並列比較: EPM5192AQM100-20 メーカー: Intel および EPM5192AQM100-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera
EPM5192AQM100-20 Obsolete仕様比較
| パラメータ | EPM5192AQM100-20 | EPM5192AQM100-15 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.20 | $16.20 |
| Device Family | MAX 5000 (EPLD / classic CPLD) | — |
| Logic Elements | 192 macrocells across 12 Logic Array Blocks (LABs) | — |
| Number of LABs | 12 | — |
| User I/O Lines | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Pin-to-Pin Propagation Delay (tPD) | 33 ns | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| パッケージ | 100-pin PQFP (JESD-30 code R-PQFP-G100) | PQFP-100 (R-PQFP-G100) |
| 実装タイプ | Surface Mount | Surface Mount |
| Process Technology | CMOS EPROM-based | CMOS |
| Configuration Memory | On-chip EPROM (non-volatile, one-time programmable in this package) | — |
| Boundary-Scan Test | JTAG / IEEE 1149.1 compatible | — |
| External Clock Input | Yes (global clock pin) | — |
| Operating Temperature Grade | [DATA_NEEDED: explicit temperature grade from datasheet] | — |
| 電源電圧 | [DATA_NEEDED: VCC range from datasheet] | 5 V (typical, single supply) |
| RoHS ステータス | [DATA_NEEDED: verified from manufacturer product page] | [DATA_NEEDED: RoHS status] |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable PLD) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect Architecture | — | Product Term Sharing (PIA) |
| User I/O Pins | — | 64 |
| Total Inputs | — | 72 |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| Speed Grade | — | -15 (15 ns macrocell delay) |
| Programming Technology | — | EPROM (UV-erasable) |
| 動作温度 | — | [DATA_NEEDED: operating temperature range] |