EPM5192JC vs EPM5192JC68 比較
詳細な並列比較: EPM5192JC メーカー: Intel および EPM5192JC68 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192JC | EPM5192JC68 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $16.40 | $15.85 |
| Product Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Series | EPM5192 (Classic / MAX-class) | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect Architecture | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| パッケージ | 68-pin PLCC (JC) windowed ceramic | — |
| 実装タイプ | Surface Mount | Surface Mount (PLCC socket compatible) |
| Programming Method | UV-erase + EPROM programmer | — |
| Non-Volatile Configuration | Yes (EPROM cell array) | — |
| Logic Family | Classic CPLD (EPM5xxx series) | — |
| 動作温度 | [DATA_NEEDED: commercial / industrial / military grade] | 0C to 70C (commercial, JC suffix) |
| 電源電圧 | [DATA_NEEDED: VCC nominal] | [DATA_NEEDED: VCC] |
| Propagation Delay | [DATA_NEEDED: tpd spec by speed grade] | — |
| RoHS ステータス | [DATA_NEEDED: original Altera marking not RoHS] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Logic Elements / Macrocells | — | 192 macrocells |
| User I/O Pins | — | 76 |
| ピン数 | — | 68 |
| Package Type | — | PLCC-68 (J-Lead) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX] |
| Configuration Memory | — | UV-Erasable EPROM |
| Programmable Interconnect | — | Programmable Logic Array + Macrocells |
| Dedicated Inputs | — | 12 |
| Clock Pins | — | 4 dedicated |
| Programming Tool | — | MAX+PLUS II (legacy) |