EPM5192JI vs EPM5192GC-2 比較
詳細な並列比較: EPM5192JI メーカー: Altera および EPM5192GC-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192JI | EPM5192GC-2 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.75 | $92.00 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-erasable CMOS Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Propagation Delay (tpd) | 55 ns | — |
| 電源電圧 | 4.75 V to 5.25 V (nominal 5 V) | — |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| パッケージ | 84-pin PLCC (windowed, J-suffix ceramic) | — |
| 動作温度 | -40 C to +125 C (industrial, I-suffix) | Commercial (0C to +70C) |
| 実装タイプ | Surface Mount (PLCC socket recommended for UV erasure) | Through-hole (PGA socket) |
| RoHS ステータス | [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) |
| Programming Method | Altera MAX 5000 programming algorithm (device programmer) | — |
| Erasure Method | UV exposure through windowed package | — |
| Logic Array Blocks | — | 16 (LABs of 16 macrocells each) |
| Usable I/O Pins | — | [DATA_NEEDED: exact user I/O count for PGA package] |
| Propagation Delay (tPD) | — | 12 ns typical (-2 grade) |
| Counter Frequency | — | 100 MHz minimum |
| Supply Voltage (VCC) | — | 5 V nominal |
| Programmable Technology | — | UV-erasable / one-time programmable |
| Programming Toolchain | — | Altera MAX+PLUS II |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| Speed Grade | — | -2 |