EPM5192JI vs EPM5192GC-2 Comparação
Comparação detalhada lado a lado de EPM5192JI por Altera e EPM5192GC-2 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM5192JI | EPM5192GC-2 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,75 | $92,00 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-erasable CMOS Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Propagation Delay (tpd) | 55 ns | — |
| Tensão de alimentação | 4.75 V to 5.25 V (nominal 5 V) | — |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| Encapsulamento | 84-pin PLCC (windowed, J-suffix ceramic) | — |
| Temperatura de operação | -40 C to +125 C (industrial, I-suffix) | Commercial (0C to +70C) |
| Tipo de montagem | Surface Mount (PLCC socket recommended for UV erasure) | Through-hole (PGA socket) |
| Status RoHS | [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) |
| Programming Method | Altera MAX 5000 programming algorithm (device programmer) | — |
| Erasure Method | UV exposure through windowed package | — |
| Logic Array Blocks | — | 16 (LABs of 16 macrocells each) |
| Usable I/O Pins | — | [DATA_NEEDED: exact user I/O count for PGA package] |
| Propagation Delay (tPD) | — | 12 ns typical (-2 grade) |
| Counter Frequency | — | 100 MHz minimum |
| Supply Voltage (VCC) | — | 5 V nominal |
| Programmable Technology | — | UV-erasable / one-time programmable |
| Programming Toolchain | — | Altera MAX+PLUS II |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| Speed Grade | — | -2 |