EPM5192LC84-2 vs EPM5192LC84-1 比較
詳細な並列比較: EPM5192LC84-2 メーカー: Altera および EPM5192LC84-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192LC84-2 | EPM5192LC84-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.10 | $21.85 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable / OTP Complex PLD) | EPLD (UV-Erasable / OTP Complex PLD) |
| Macrocells | 192 | 192 |
| パッケージ | 84-pin PLCC (LC) | 84-pin PLCC (LC84) |
| Speed Grade | -2 | -1 |
| 電源電圧 | 5 V (TTL-compatible I/O) | — |
| Technology | CMOS, UV-erasable / OTP | — |
| Logic Elements | AND-OR array with macrocell flip-flops | — |
| Programming Method | Altera legacy programmer (JEDEC bitstream) | — |
| 動作温度 | Commercial (0C to +70C) | 0C to +70C (commercial) |
| 実装タイプ | Surface Mount | Surface Mount (J-lead) |
| RoHS ステータス | Non-compliant (SnPb lead finish typical for this vintage) | [DATA_NEEDED: not stated in provided data] |
| ライフサイクル状態 | Obsolete (last Altera MAX 5000 production) | — |
| JTAG Support | Vendor-specific programming interface (pre-IEEE 1532) | — |
| I/O Standard | TTL, 5V CMOS-compatible | — |
| Logic Array Blocks (LABs) | — | 16 |
| Usable Gates | — | 7,500 |
| Propagation Delay (tPD) | — | [DATA_NEEDED: tPD ns value] |
| Supply Voltage (VCC) | — | 5 V |
| Program Memory Type | — | UV-EPROM / OTP |
| I/O Count | — | [DATA_NEEDED: I/O pin count] |
| Process Technology | — | CMOS EPROM |