EPM570T100C3 vs EPM570T100C3N 比較
詳細な並列比較: EPM570T100C3 メーカー: Intel および EPM570T100C3N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM570T100C3 | EPM570T100C3N |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.50 | $8.10 |
| Family | MAX II | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements | 570 | — |
| Equivalent Macrocells | 440 | — |
| User I/O Pins | 76 (max) | — |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits |
| Maximum Operating Frequency | 304 MHz | — |
| Technology Node | 0.18 µm 6-layer-metal flash process | — |
| Internal Supply Voltage | 2.5 V / 3.3 V | — |
| I/O Voltage Support (MultiVolt) | 1.5 V, 1.8 V, 2.5 V, 3.3 V | — |
| パッケージ | 100-pin TQFP (T100), 14×14 mm | 100-TQFP (T100) |
| Temperature Grade | Commercial (C) | — |
| Speed Grade | 3 (fastest C-grade) | C3 |
| Programming | In-System Programmable (ISP) via JTAG (IEEE 1149.1) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | Compliant | Compliant |
| Macro Cells | — | 440 |
| Logic Elements (LEs) | — | 570 |
| Maximum User I/Os | — | 76 |
| Pin-to-Pin Delay (tPD1) | — | 5.4 ns |
| Maximum Internal Frequency | — | 304 MHz |
| Number of LABs | — | 57 |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V (MultiVolt) |
| Process Technology | — | 0.18 µm Flash |
| 動作温度 | — | 0 °C to +85 °C (Commercial) |
| Programming Interface | — | JTAG / IEEE 1149.1 boundary-scan |
| In-System Programmable | — | Yes |