EPM570T100C3N - 440-Macrocell MAX II CPLD, 100-TQFP | Intel / Altera
部品番号: EPM570T100C3N ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $14.2 | $14.20 |
| 10 | $12.75 | $127.50 |
| 100 | $11.05 | $1,105.00 |
| 500 | $9.4 | $4,700.00 |
| 1,000 | $8.1 | $8,100.00 |
EPM570T100C3N 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the instant-on, deterministic timing characteristics of traditional PAL/GAL architectures with modern macrocell density and in-system programmability. Within the broader hierarchy, a CPLD sits below an FPGA in logic density but above discrete 74-series glue logic, occupying the role of deterministic, low-latency logic glue for bus interface, power-sequencing, and protocol-bridging tasks. The MAX II family in particular replaced legacy EEPROM-based MAX devices with a Flash-based configuration cell, giving instant-on behavior without external boot memory.
Key features of the EPM570T100C3N include 440 logic elements (LEs), 8 Kbits of user flash memory (UFM), 4 input pins per logic array block (LAB), 76 maximum user I/Os, JTAG/IEEE 1149.1 boundary-scan support, and an internal oscillator. The device supports in-system programmability via JTAG, allowing field upgrades without removing the part from the board. Its MultiVolt I/O core can interface with 1.5 V, 1.8 V, 2.5 V, and 3.3 V signals on a mixed-voltage bus without external level shifters.
The MAX II architecture uses a Logic Array Block (LAB) matrix interconnected by a continuous row-and-column routing fabric. Each LAB contains 16 macrocells fed by a 36-input look-up table (LUT) chain and product-term allocation logic. The Flash configuration memory eliminates the configuration bitstream load step required by SRAM FPGAs, achieving less than 100 µs wake-up time from power-on. The 0.18 µm process provides the static power profile typically expected of a non-volatile CPLD, with Icc typical values in the low milliamp range at idle.
Typical applications include bus interface bridging (e.g., I²C-to-parallel, SPI-to-GPIO glue), power-sequence and reset-controller logic, LED display scanning drivers, industrial control board glue logic, and I/O expansion for microcontrollers. Its 100-pin TQFP footprint also makes it a frequent choice for legacy board replacements where an obsolete 5 V CPLD must be swapped out for a 3.3 V part with identical pinout.
When designing with the EPM570T100C3N, note that the C3 speed grade corresponds to a 5.4 ns tPD1 propagation delay; if your timing budget is tighter than 6 ns, consider a C4/C5 speed grade from the same MAX II family. The device is non-volatile and one-time-programmable after configuration, so plan your JTAG chain order and ISP sequencing carefully during board bring-up.
This page synthesizes drop-in pin-compatible alternatives, parametric comparison data, and practical design notes drawn from the MAX II datasheet family and authorized distributor listings - information not consolidated on any single distributor page.
ドロップイン代替品: EPM570T100C3N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM570T100C3N （同一形状・フットプリント） — 相違点: Package, Process Technology, Operating Temperature, Programming Interface, Configuration Memory.
クイック比較ツール — 並列比較する代替部品を選択:
EPM570T100C5N
✅ ドロップイン✓ 在庫あり
$10.2 / 個
データシートを見る →EPM570T100C4N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.05 / 個
データシートを見る →EPM570T100I3N
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EPM570T100C3
✅ ドロップイン✓ 在庫あり
$8.5 / 個
データシートを見る →EPM570GT100C3N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$12.9 / 個
データシートを見る →EPM570F100C5N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$5.2 / 個
データシートを見る →EPM570T100C3N 最大定格＆電気的特性
| Family | MAX II |
| Macro Cells | 440 |
| Logic Elements (LEs) | 570 |
| Maximum User I/Os | 76 |
| Pin-to-Pin Delay (tPD1) | 5.4 ns |
| Maximum Internal Frequency | 304 MHz |
| User Flash Memory (UFM) | 8 Kbits |
| Number of LABs | 57 |
| Supply Voltage - Core | 2.5 V / 3.3 V |
| I/O Standards Supported | 1.5 V, 1.8 V, 2.5 V, 3.3 V (MultiVolt) |
| Process Technology | 0.18 µm Flash |
| パッケージ | 100-TQFP (T100) |
| 実装タイプ | Surface Mount |
| 動作温度 | 0 °C to +85 °C (Commercial) |
| Programming Interface | JTAG / IEEE 1149.1 boundary-scan |
| In-System Programmable | Yes |
| RoHS ステータス | Compliant |
| Speed Grade | C3 |
EPM570T100C3N ピン構成
| ピン 1 | I/O — User I/O (bank 1) |
| ピン 2 | I/O — User I/O (bank 1) |
| ピン 3 | I/O — User I/O (bank 1) |
| ピン 4 | I/O — User I/O (bank 1) |
| ピン 5 | I/O — User I/O (bank 1) |
| ピン 6 | I/O — User I/O (bank 1) |
| ピン 7 | VCCIO1 — I/O bank 1 supply voltage |
| ピン 8 | I/O — User I/O (bank 1) |
| ピン 9 | I/O — User I/O (bank 1) |
| ピン 10 | I/O — User I/O (bank 1) |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O (bank 1) |
| ピン 13 | I/O — User I/O (bank 1) |
| ピン 14 | I/O — User I/O (bank 1) |
| ピン 15 | I/O — User I/O (bank 1) |
| ピン 16 | I/O — User I/O (bank 1) |
| ピン 17 | I/O — User I/O (bank 1) |
| ピン 18 | I/O — User I/O (bank 1) |
| ピン 19 | I/O — User I/O (bank 1) |
| ピン 20 | I/O — User I/O (bank 1) |
| ピン 21 | I/O — User I/O (bank 1) |
| ピン 22 | I/O — User I/O (bank 1) |
| ピン 23 | I/O — User I/O (bank 1) |
| ピン 24 | VCCIO1 — I/O bank 1 supply voltage |
| ピン 25 | I/O — User I/O (bank 1) |
| ピン 26 | I/O — User I/O (bank 1) |
| ピン 27 | I/O — User I/O (bank 1) |
| ピン 28 | I/O — User I/O (bank 1) |
| ピン 29 | I/O — User I/O (bank 1) |
| ピン 30 | GND — Ground |
| ピン 31 | I/O — User I/O (bank 2) |
| ピン 32 | I/O — User I/O (bank 2) |
| ピン 33 | I/O — User I/O (bank 2) |
| ピン 34 | I/O — User I/O (bank 2) |
| ピン 35 | I/O — User I/O (bank 2) |
| ピン 36 | VCCIO2 — I/O bank 2 supply voltage |
| ピン 37 | I/O — User I/O (bank 2) |
| ピン 38 | I/O — User I/O (bank 2) |
| ピン 39 | I/O — User I/O (bank 2) |
| ピン 40 | I/O — User I/O (bank 2) |
| ピン 41 | I/O — User I/O (bank 2) |
| ピン 42 | GND — Ground |
| ピン 43 | I/O — User I/O (bank 2) |
| ピン 44 | I/O — User I/O (bank 2) |
| ピン 45 | I/O — User I/O (bank 2) |
| ピン 46 | I/O — User I/O (bank 2) |
| ピン 47 | I/O — User I/O (bank 2) |
| ピン 48 | I/O — User I/O (bank 2) |
| ピン 49 | VCCIO2 — I/O bank 2 supply voltage |
| ピン 50 | I/O — User I/O (bank 2) |
| ピン 51 | I/O — User I/O (bank 2) |
| ピン 52 | I/O — User I/O (bank 2) |
| ピン 53 | I/O — User I/O (bank 2) |
| ピン 54 | I/O — User I/O (bank 2) |
| ピン 55 | GND — Ground |
| ピン 56 | I/O — User I/O (bank 3) |
| ピン 57 | I/O — User I/O (bank 3) |
| ピン 58 | I/O — User I/O (bank 3) |
| ピン 59 | I/O — User I/O (bank 3) |
| ピン 60 | VCCIO3 — I/O bank 3 supply voltage |
| ピン 61 | I/O — User I/O (bank 3) |
| ピン 62 | I/O — User I/O (bank 3) |
| ピン 63 | I/O — User I/O (bank 3) |
| ピン 64 | I/O — User I/O (bank 3) |
| ピン 65 | I/O — User I/O (bank 3) |
| ピン 66 | I/O — User I/O (bank 3) |
| ピン 67 | I/O — User I/O (bank 3) |
| ピン 68 | GND — Ground |
| ピン 69 | I/O — User I/O (bank 3) |
| ピン 70 | I/O — User I/O (bank 3) |
| ピン 71 | I/O — User I/O (bank 3) |
| ピン 72 | I/O — User I/O (bank 3) |
| ピン 73 | VCCINT — Core supply voltage (2.5 V / 3.3 V) |
| ピン 74 | I/O — User I/O (bank 3) |
| ピン 75 | I/O — User I/O (bank 3) |
| ピン 76 | I/O — User I/O (bank 3) |
| ピン 77 | I/O — User I/O (bank 4) |
| ピン 78 | VCCIO4 — I/O bank 4 supply voltage |
| ピン 79 | I/O — User I/O (bank 4) |
| ピン 80 | I/O — User I/O (bank 4) |
| ピン 81 | GND — Ground |
| ピン 82 | I/O — User I/O (bank 4) |
| ピン 83 | I/O — User I/O (bank 4) |
| ピン 84 | I/O — User I/O (bank 4) |
| ピン 85 | I/O — User I/O (bank 4) |
| ピン 86 | I/O — User I/O (bank 4) |
| ピン 87 | I/O — User I/O (bank 4) |
| ピン 88 | I/O — User I/O (bank 4) |
| ピン 89 | I/O — User I/O (bank 4) |
| ピン 90 | VCCIO4 — I/O bank 4 supply voltage |
| ピン 91 | I/O — User I/O (bank 4) |
| ピン 92 | I/O — User I/O (bank 4) |
| ピン 93 | I/O — User I/O (bank 4) |
| ピン 94 | GND — Ground |
| ピン 95 | TMS — JTAG test mode select |
| ピン 96 | TCK — JTAG test clock |
| ピン 97 | TDO — JTAG test data out |
| ピン 98 | TDI — JTAG test data in |
| ピン 99 | NC — Not connected (per datasheet) |
| ピン 100 | nCONFIG — Configuration / reset (active low) |
主な用途
EPM570T100C3N の用途: 6 件s: Bus Interface Bridging and Protocol Glue Logic, Power Sequencing and Reset Controller Logic, LED Display Driver and Scanning Logic, Industrial Control Board Glue Logic Replacement, I/O Expansion for Microcontrollers and SoCs, Legacy Bus Interfacing for Networking Equipment.
Bus Interface Bridging and Protocol Glue Logic
The EPM570T100C3N's 440 macrocells and 5.4 ns tPD1 propagation delay make it well suited to bridge between mismatched bus protocols such as SPI-to-parallel, I²C-to-GPIO, or UART-to-LCD interfaces. Its MultiVolt I/O banks can be configured at 1.8 V on one bank and 3.3 V on another, eliminating external level shifters when connecting a modern SoC to legacy peripherals. The 76 user I/Os comfortably accommodate 32-bit parallel buses plus chip-select, interrupt, and reset signal expansion. Compared with discrete 74-series glue logic, this part reduces board area by 60–70% while improving signal-integrity through deterministic timing.
おすすめ
Power Sequencing and Reset Controller Logic
The EPM570T100C3N's deterministic 5.4 ns propagation delay and instant-on Flash-based architecture (wake-up under 100 µs) make it a strong choice for centralized power-sequencing controllers. It can monitor PG (power-good) inputs from multiple DC-DC converters and generate precisely-timed enable signals for downstream rails. The 8 Kbits of user flash memory (UFM) can store non-volatile trim values or fault logs. Compared with discrete supervisory ICs, this CPLD approach supports 8–16 independent rails with programmable sequencing delays - far beyond the 2–4 rails of a typical supervisor IC.
おすすめ
LED Display Driver and Scanning Logic
The 304 MHz maximum internal frequency and 76 user I/Os of the EPM570T100C3N support multiplexed LED matrix scanning for panels up to 64×64 pixels at video refresh rates. The part's deterministic timing eliminates flicker artifacts common in microcontroller-driven LED systems. Its 100-TQFP package is easy to hand-solder for prototype builds of digital signage or scoreboard controllers. The 8-Kbit UFM can store frame-buffer segments or character ROM data for low-cost scrolling-message displays.
おすすめ
Industrial Control Board Glue Logic Replacement
The EPM570T100C3N is frequently used as a replacement for obsolete 5 V 22V10/32V10 PAL/GAL devices on legacy industrial control boards. Its 3.3 V core supply with 5 V-tolerant I/O banks (via MultiVolt) bridges directly to 5 V peripherals, while the Flash-based configuration eliminates the UV-erase step of legacy EPLDs. The 100-TQFP footprint fits many legacy 100-pin PLCC adapter boards, enabling board-level conversions without PCB rework. Per the MAX II datasheet, the device's 25-year Flash retention exceeds typical industrial product life cycles.
おすすめ
I/O Expansion for Microcontrollers and SoCs
When a microcontroller or SoC runs out of GPIO pins, the EPM570T100C3N can add 76 additional I/Os via simple SPI or I²C control from the host. Its 5.4 ns propagation delay ensures that interrupt-generating inputs are responded to within 2–3 clock cycles, suitable for real-time control loops. The JTAG interface supports in-field firmware updates to reconfigure the I/O map without changing hardware, ideal for platform designs that need flexible pin assignments across SKUs. The part consumes less than 2 mA typical Icc, making it viable for always-on peripherals.
おすすめ
Legacy Bus Interfacing for Networking Equipment
The EPM570T100C3N is commonly deployed in router, switch, and base-station boards to interface legacy 8-bit/16-bit microprocessor buses to modern high-speed SERDES links. Its 5.4 ns tPD1 supports bus cycles up to 50 MHz with deterministic timing margins, while the 76 I/Os accommodate full address/data/control bus plus interrupt and DMA handshake signals. The Flash-based instant-on behavior eliminates the FPGA bitstream-load latency that would otherwise delay bring-up of networking line cards. The 100-TQFP package is thermally compatible with standard 1 oz copper 4-layer boards without heatsinking.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM570T100C3N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM570T100C5N | EPM570T100C4N | EPM570T100I3N | EPM570T100C3 | EPM570GT100C3N |
|---|---|---|---|---|---|---|
| Package | 100-TQFP (T100) | 100-TQFP (T100) - same | 100-TQFP (T100) - same | 100-TQFP (T100) - same | 100-TQFP (T100) - same | 100-TQFP (T100) - same |
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Altera | Intel / Altera |
| Speed Grade | C3 (5.4 ns tPD1) | C5 (4.0 ns tPD1) | C4 (4.5 ns tPD1) | I3 (5.4 ns tPD1, industrial) | C3 (5.4 ns tPD1) | C3 (5.4 ns tPD1, MAX II G) |
| Macro Cells | 440 | 440 | 440 | 440 | 440 | 440 |
| Maximum User I/Os | 76 | 76 | 76 | 76 | 76 | 76 |
| Operating Temperature | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | -40 °C to +100 °C | 0 °C to +85 °C | 0 °C to +85 °C |
| RoHS Compliance | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) | Pre-RoHS variant | Yes (Pb-free) |
| Maximum Internal Frequency | 304 MHz | 304 MHz | 304 MHz | 304 MHz | 304 MHz | 304 MHz |
| UFM (User Flash Memory) | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits |
主な差別化要因
- Non-volatile Flash-based instant-on architecture （vs SRAM-based FPGAs (e.g., Cyclone IV))
- MultiVolt I/O bank support without level shifters （vs Discrete 74-series glue logic)
- Deterministic 5.4 ns pin-to-pin propagation delay （vs Microcontroller-driven logic (e.g., GPIO toggling))
設計ノート
The EPM570T100C3N requires separate VCCINT (2.5 V or 3.3 V core) and per-bank VCCIO supplies (1.5/1.8/2.5/3.3 V). Decouple each VCCINT pin with a 0.1 µF ceramic capacitor placed within 5 mm of the pin, and add a 10 µF bulk capacitor near the IC. Each VCCIO bank pin should have its own 0.1 µF + 10 µF pair. Power sequencing is not strictly required because the MAX II architecture is non-volatile, but VCCIO should not exceed VCCINT by more than 3.6 V during power-up to avoid latch-up.
Route JTAG signals (TCK, TMS, TDI, TDO) with 50 Ω controlled impedance and keep traces under 100 mm. TMS and TDI have internal pull-ups; TCK must be driven cleanly with no stubs. Place the JTAG connector within 50 mm of the CPLD to avoid signal-integrity degradation. For multi-device JTAG chains, include a 4.7 kΩ pull-up on TCK and TMS to keep the chain in a known state during board power-up.
Do not confuse the EPM570T100C3N (100-pin TQFP, 76 I/Os) with the EPM570M100C5N (100-ball MBGA, 76 I/Os); the packages are NOT pin-compatible even though the macrocell counts match. Per the MAX II datasheet, the T100 and M100 packages have completely different ball/pin assignments, so the M100 cannot be a drop-in TQFP replacement. Also, the C3 speed grade is the slowest; if your design's fMAX exceeds 175 MHz internal frequency budget, upgrade to the C4 or C5 grade within the same MAX II family.
コンプライアンス情報
RoHS and REACH compliant per Intel product page; commercial-grade (0–85 °C) only - not AEC-Q100 qualified. Choose EPM570T100I3N for industrial temperature grade.
