EPM570T144-5 vs EPM570T144C4N 比較
詳細な並列比較: EPM570T144-5 メーカー: Altera および EPM570T144C4N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM570T144-5 | EPM570T144C4N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.85 | $25.10 |
| Family | MAX II | MAX II |
| Device | EPM570 | — |
| Logic Elements (LE) | 570 | 570 |
| Macrocells (typical) | 440 | — |
| User I/O Pins | 116 | — |
| パッケージ | TQFP-144 (T144) | TQFP-144 (22 × 22 mm, 0.5 mm pitch) |
| ピン数 | 144 | — |
| Speed Grade | -5 (≈5.0 ns tPD1) | — |
| Process Technology | 0.18 µm | 0.18 µm flash CMOS, 6-layer metal |
| Non-volatile Configuration | Internal Flash (instant-on) | — |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits |
| I/O Banks | 4 | — |
| MultiVolt I/O Support | 1.5 V, 1.8 V, 2.5 V, 3.3 V | — |
| VCCINT | 3.3 V or 2.5 V (per bank group) | — |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | JTAG (IEEE 1149.1) with in-system programmability (ISP) |
| 動作温度 | [DATA_NEEDED: temperature grade for -5 suffix] | -40 °C to +85 °C (industrial, suffix N) |
| RoHS ステータス | Depends on date code (pre-2010 lots non-RoHS; lead-free Pb-free opt. available) | — |
| Equivalent Macrocells | — | 440 |
| Maximum User I/O Pins | — | 212 (package-dependent; TQFP-144 user count varies) |
| Maximum Internal Frequency (fMAX) | — | 247.5 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 5.4 ns (C4 speed grade) |
| Core Supply Voltage (VCCINT) | — | 2.5 V / 3.3 V (MultiVolt core) |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) |
| 実装タイプ | — | Surface Mount |
| MSLレベル | — | 3 (per JEDEC J-STD-020) |
| Lead-Free / RoHS | — | Lead-free, RoHS compliant |
| Global Clock Networks | — | 4 |
| Non-Volatile Configuration | — | Yes (instant-on, no external boot PROM required) |