EPM570T144C4N - 570 LE MAX II CPLD, 144-TQFP | Intel
部品番号: EPM570T144C4N ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $36.15 | $36.15 |
| 10 | $33.2 | $332.00 |
| 100 | $29.85 | $2,985.00 |
| 500 | $27.4 | $13,700.00 |
| 1,000 | $25.1 | $25,100.00 |
EPM570T144C4N 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits in the hierarchy between simple logic gates and full FPGAs. Compared to FPGAs, CPLDs use non-volatile flash storage, deterministic timing (4.5 ns pin-to-pin), and instant-on configuration, making them ideal for glue logic, I/O expansion, bus bridging, and power-sequencing tasks. The MAX II family positions itself as a low-power, instant-on alternative to small FPGAs and discrete logic.
Key features include a 247.5 MHz internal frequency, 5.4 ns tPD (pin-to-pin propagation delay), 0.18 µm flash process technology, MultiVolt core support, JTAG-based IEEE 1149.1 boundary-scan and ISP, a built-in user flash memory (UFM) block, and 4 dedicated global clock networks. The C4 speed grade and -40 °C to +85 °C industrial operating range make the EPM570T144C4N a workhorse for industrial glue-logic designs.
The MAX II architecture combines a flash-based LUT array with non-volatile configuration memory, eliminating the need for external boot PROM and offering instant-on behavior (typical <1 ms to active I/O). The MultiVolt I/O ring allows direct interfacing with 1.5V, 1.8V, 2.5V, 3.3V, and 5.0V systems without external level shifters, simplifying mixed-voltage board design.
Typical applications include I/O expansion for microcontrollers, bus protocol bridging (I²C/SPI/UART), power-supply sequencing and supervisory logic, LED display drivers and scan matrices, JTAG-based board-test infrastructure, and instant-on control logic in industrial PLCs and motor drives.
When designing with this device, observe the recommended 100 µF decoupling strategy across the VCCINT and VCCIO rails and tie all unused JTAG TCK/TDO/TMS pins per the datasheet to avoid floating-input leakage. Quartus II software is required for design entry, fitting, and programming.
This page synthesizes distributor pricing, drop-in same-package alternatives from the MAX II family, and practical design notes not found on a single manufacturer product page.
ドロップイン代替品: EPM570T144C4N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM570T144C4N （同一形状・フットプリント） — 相違点: Programming Interface, Package, Operating Temperature, Process Technology, Configuration Memory.
クイック比較ツール — 並列比較する代替部品を選択:
EPM570T144C4
✅ ドロップイン✓ 在庫あり
$19.2 / 個
データシートを見る →EPM570GT144C4N
✅ ドロップイン✓ 在庫あり
$22.5 / 個
データシートを見る →EPM570T144C5N
✅ ドロップイン✓ 在庫あり
$9.35 / 個
データシートを見る →EPM570T144A5N
✅ ドロップイン✓ 在庫あり
$22.8 / 個
データシートを見る →EPM570T144C3N
✅ ドロップイン✓ 在庫あり
$9.6 / 個
データシートを見る →EPM570T144C4N 最大定格＆電気的特性
| Family | MAX II |
| Logic Elements (LE) | 570 |
| Equivalent Macrocells | 440 |
| Maximum User I/O Pins | 212 (package-dependent; TQFP-144 user count varies) |
| User Flash Memory (UFM) | 8 Kbits |
| Process Technology | 0.18 µm flash CMOS, 6-layer metal |
| Maximum Internal Frequency (fMAX) | 247.5 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 5.4 ns (C4 speed grade) |
| Core Supply Voltage (VCCINT) | 2.5 V / 3.3 V (MultiVolt core) |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) |
| Programming Interface | JTAG (IEEE 1149.1) with in-system programmability (ISP) |
| 動作温度 | -40 °C to +85 °C (industrial, suffix N) |
| パッケージ | TQFP-144 (22 × 22 mm, 0.5 mm pitch) |
| 実装タイプ | Surface Mount |
| MSLレベル | 3 (per JEDEC J-STD-020) |
| Lead-Free / RoHS | Lead-free, RoHS compliant |
| Global Clock Networks | 4 |
| Non-Volatile Configuration | Yes (instant-on, no external boot PROM required) |
EPM570T144C4N ピン構成
| ピン 1 | I/O — General-purpose user I/O (bank 1) |
| ピン 2 | I/O — General-purpose user I/O (bank 1) |
| ピン 3 | I/O — General-purpose user I/O (bank 1) |
| ピン 4 | I/O — General-purpose user I/O (bank 1) |
| ピン 5 | I/O — General-purpose user I/O (bank 1) |
| ピン 6 | I/O — General-purpose user I/O (bank 1) |
| ピン 7 | I/O — General-purpose user I/O (bank 1) |
| ピン 8 | I/O — General-purpose user I/O (bank 1) |
| ピン 9 | I/O — General-purpose user I/O (bank 1) |
| ピン 10 | I/O — General-purpose user I/O (bank 1) |
| ピン 11 | VCCIO1 — I/O supply voltage for bank 1 (1.5V/1.8V/2.5V/3.3V) |
| ピン 12 | I/O — General-purpose user I/O (bank 1) |
| ピン 13 | I/O — General-purpose user I/O (bank 1) |
| ピン 14 | I/O — General-purpose user I/O (bank 1) |
| ピン 15 | I/O — General-purpose user I/O (bank 1) |
| ピン 16 | I/O — General-purpose user I/O (bank 1) |
| ピン 17 | I/O — General-purpose user I/O (bank 1) |
| ピン 18 | I/O — General-purpose user I/O (bank 1) |
| ピン 19 | I/O — General-purpose user I/O (bank 1) |
| ピン 20 | I/O — General-purpose user I/O (bank 1) |
| ピン 21 | GND — Ground |
| ピン 22 | I/O — General-purpose user I/O (bank 2) |
| ピン 23 | I/O — General-purpose user I/O (bank 2) |
| ピン 24 | I/O — General-purpose user I/O (bank 2) |
| ピン 25 | I/O — General-purpose user I/O (bank 2) |
| ピン 26 | I/O — General-purpose user I/O (bank 2) |
| ピン 27 | I/O — General-purpose user I/O (bank 2) |
| ピン 28 | I/O — General-purpose user I/O (bank 2) |
| ピン 29 | I/O — General-purpose user I/O (bank 2) |
| ピン 30 | I/O — General-purpose user I/O (bank 2) |
| ピン 31 | I/O — General-purpose user I/O (bank 2) |
| ピン 32 | I/O — General-purpose user I/O (bank 2) |
| ピン 33 | VCCIO2 — I/O supply voltage for bank 2 (1.5V/1.8V/2.5V/3.3V) |
| ピン 34 | I/O — General-purpose user I/O (bank 2) |
| ピン 35 | I/O — General-purpose user I/O (bank 2) |
| ピン 36 | I/O — General-purpose user I/O (bank 2) |
| ピン 37 | I/O — General-purpose user I/O (bank 2) |
| ピン 38 | I/O — General-purpose user I/O (bank 2) |
| ピン 39 | I/O — General-purpose user I/O (bank 2) |
| ピン 40 | I/O — General-purpose user I/O (bank 2) |
| ピン 41 | I/O — General-purpose user I/O (bank 2) |
| ピン 42 | GND — Ground |
| ピン 43 | I/O — General-purpose user I/O (bank 3) |
| ピン 44 | I/O — General-purpose user I/O (bank 3) |
| ピン 45 | I/O — General-purpose user I/O (bank 3) |
| ピン 46 | I/O — General-purpose user I/O (bank 3) |
| ピン 47 | I/O — General-purpose user I/O (bank 3) |
| ピン 48 | I/O — General-purpose user I/O (bank 3) |
| ピン 49 | I/O — General-purpose user I/O (bank 3) |
| ピン 50 | I/O — General-purpose user I/O (bank 3) |
| ピン 51 | I/O — General-purpose user I/O (bank 3) |
| ピン 52 | I/O — General-purpose user I/O (bank 3) |
| ピン 53 | I/O — General-purpose user I/O (bank 3) |
| ピン 54 | I/O — General-purpose user I/O (bank 3) |
| ピン 55 | VCCIO3 — I/O supply voltage for bank 3 (1.5V/1.8V/2.5V/3.3V) |
| ピン 56 | I/O — General-purpose user I/O (bank 3) |
| ピン 57 | I/O — General-purpose user I/O (bank 3) |
| ピン 58 | I/O — General-purpose user I/O (bank 3) |
| ピン 59 | I/O — General-purpose user I/O (bank 3) |
| ピン 60 | I/O — General-purpose user I/O (bank 3) |
| ピン 61 | I/O — General-purpose user I/O (bank 3) |
| ピン 62 | I/O — General-purpose user I/O (bank 3) |
| ピン 63 | I/O — General-purpose user I/O (bank 3) |
| ピン 64 | GND — Ground |
| ピン 65 | I/O — General-purpose user I/O (bank 4) |
| ピン 66 | I/O — General-purpose user I/O (bank 4) |
| ピン 67 | I/O — General-purpose user I/O (bank 4) |
| ピン 68 | I/O — General-purpose user I/O (bank 4) |
| ピン 69 | I/O — General-purpose user I/O (bank 4) |
| ピン 70 | I/O — General-purpose user I/O (bank 4) |
| ピン 71 | I/O — General-purpose user I/O (bank 4) |
| ピン 72 | I/O — General-purpose user I/O (bank 4) |
| ピン 73 | I/O — General-purpose user I/O (bank 4) |
| ピン 74 | I/O — General-purpose user I/O (bank 4) |
| ピン 75 | I/O — General-purpose user I/O (bank 4) |
| ピン 76 | I/O — General-purpose user I/O (bank 4) |
| ピン 77 | VCCIO4 — I/O supply voltage for bank 4 (1.5V/1.8V/2.5V/3.3V) |
| ピン 78 | I/O — General-purpose user I/O (bank 4) |
| ピン 79 | I/O — General-purpose user I/O (bank 4) |
| ピン 80 | I/O — General-purpose user I/O (bank 4) |
| ピン 81 | I/O — General-purpose user I/O (bank 4) |
| ピン 82 | I/O — General-purpose user I/O (bank 4) |
| ピン 83 | I/O — General-purpose user I/O (bank 4) |
| ピン 84 | I/O — General-purpose user I/O (bank 4) |
| ピン 85 | I/O — General-purpose user I/O (bank 4) |
| ピン 86 | GND — Ground |
| ピン 87 | TDI — JTAG Test Data In (with internal weak pull-up) |
| ピン 88 | TMS — JTAG Test Mode Select (with internal weak pull-up) |
| ピン 89 | TCK — JTAG Test Clock (with internal weak pull-down) |
| ピン 90 | TDO — JTAG Test Data Out |
| ピン 91 | I/O — General-purpose user I/O (bank 4) |
| ピン 92 | I/O — General-purpose user I/O (bank 4) |
| ピン 93 | I/O — General-purpose user I/O (bank 4) |
| ピン 94 | I/O — General-purpose user I/O (bank 4) |
| ピン 95 | I/O — General-purpose user I/O (bank 4) |
| ピン 96 | I/O — General-purpose user I/O (bank 4) |
| ピン 97 | I/O — General-purpose user I/O (bank 4) |
| ピン 98 | I/O — General-purpose user I/O (bank 4) |
| ピン 99 | I/O — General-purpose user I/O (bank 4) |
| ピン 100 | I/O — General-purpose user I/O (bank 4) |
| ピン 101 | VCCINT — Core supply voltage (2.5V or 3.3V) |
| ピン 102 | GND — Ground |
| ピン 103 | I/O — General-purpose user I/O (bank 3) |
| ピン 104 | I/O — General-purpose user I/O (bank 3) |
| ピン 105 | I/O — General-purpose user I/O (bank 3) |
| ピン 106 | I/O — General-purpose user I/O (bank 3) |
| ピン 107 | I/O — General-purpose user I/O (bank 3) |
| ピン 108 | I/O — General-purpose user I/O (bank 3) |
| ピン 109 | I/O — General-purpose user I/O (bank 3) |
| ピン 110 | I/O — General-purpose user I/O (bank 3) |
| ピン 111 | I/O — General-purpose user I/O (bank 3) |
| ピン 112 | I/O — General-purpose user I/O (bank 3) |
| ピン 113 | I/O — General-purpose user I/O (bank 3) |
| ピン 114 | I/O — General-purpose user I/O (bank 3) |
| ピン 115 | I/O — General-purpose user I/O (bank 3) |
| ピン 116 | I/O — General-purpose user I/O (bank 3) |
| ピン 117 | I/O — General-purpose user I/O (bank 3) |
| ピン 118 | I/O — General-purpose user I/O (bank 3) |
| ピン 119 | I/O — General-purpose user I/O (bank 3) |
| ピン 120 | I/O — General-purpose user I/O (bank 3) |
| ピン 121 | I/O — General-purpose user I/O (bank 2) |
| ピン 122 | I/O — General-purpose user I/O (bank 2) |
| ピン 123 | I/O — General-purpose user I/O (bank 2) |
| ピン 124 | I/O — General-purpose user I/O (bank 2) |
| ピン 125 | I/O — General-purpose user I/O (bank 2) |
| ピン 126 | I/O — General-purpose user I/O (bank 2) |
| ピン 127 | I/O — General-purpose user I/O (bank 2) |
| ピン 128 | I/O — General-purpose user I/O (bank 2) |
| ピン 129 | I/O — General-purpose user I/O (bank 2) |
| ピン 130 | I/O — General-purpose user I/O (bank 2) |
| ピン 131 | I/O — General-purpose user I/O (bank 2) |
| ピン 132 | I/O — General-purpose user I/O (bank 2) |
| ピン 133 | I/O — General-purpose user I/O (bank 2) |
| ピン 134 | I/O — General-purpose user I/O (bank 2) |
| ピン 135 | I/O — General-purpose user I/O (bank 1) |
| ピン 136 | I/O — General-purpose user I/O (bank 1) |
| ピン 137 | I/O — General-purpose user I/O (bank 1) |
| ピン 138 | I/O — General-purpose user I/O (bank 1) |
| ピン 139 | I/O — General-purpose user I/O (bank 1) |
| ピン 140 | I/O — General-purpose user I/O (bank 1) |
| ピン 141 | I/O — General-purpose user I/O (bank 1) |
| ピン 142 | I/O — General-purpose user I/O (bank 1) |
| ピン 143 | I/O — General-purpose user I/O (bank 1) |
| ピン 144 | GND — Ground |
主な用途
EPM570T144C4N の用途: 6 件s: Microcontroller I/O Expansion & Glue Logic, Bus Protocol Bridging (I2C/SPI/UART/CAN), Power Supply Sequencing & Supervisory Logic, LED Display Drivers & Scan Matrix Control, JTAG-Based Board Test Infrastructure (ICT/BIST), Industrial PLC & Motor Control Logic.
Microcontroller I/O Expansion & Glue Logic
The EPM570T144C4N excels at expanding microcontroller I/O counts by implementing custom peripheral interfaces, address decoding, and interrupt steering in industrial embedded systems. Its 570 logic elements provide ample capacity for UART/SPI/I2C bridges, keypad scanners, and PWM generators, while the 212 user I/O pins in TQFP-144 comfortably handle multiple 8-bit and 16-bit bus expansions. The 5.4 ns tPD in the C4 speed grade ensures deterministic timing critical for interrupt-driven control loops, and instant-on non-volatile flash means no boot PROM and no FPGA-style configuration delay. Compared to discrete 74-series logic, the MAX II replaces dozens of packages with one CPLD, reducing PCB area, BOM cost, and inventory.
おすすめ
Bus Protocol Bridging (I2C/SPI/UART/CAN)
The EPM570T144C4N is widely deployed as a bus-bridge translator between microcontrollers, sensors, and ASICs operating at mismatched voltages and protocols. Its MultiVolt I/O supports 1.5V, 1.8V, 2.5V, 3.3V, and 5.0V signaling on a per-bank basis, eliminating external level shifters. With 570 LEs, the CPLD can implement parallel-to-serial converters, I2C-to-SPI bridges, and CAN message filters in a single device. The 4.5–5.4 ns tPD keeps latency low for real-time bus arbitration. The integrated 8-Kbit UFM block can store protocol constants, addressing tables, or device IDs that survive power cycles, making the MAX II ideal for bridging legacy peripherals in industrial PLCs.
おすすめ
Power Supply Sequencing & Supervisory Logic
The EPM570T144C4N's instant-on flash-based architecture (typical <1 ms to active I/O) makes it ideal for power-supply sequencing in multi-rail systems such as FPGAs, SoCs, and RF transceivers that require strict rail-on ordering. Designers can implement PG (power-good) monitoring, watchdog timers, and reset distribution in the 570 LE fabric, replacing multiple supervisor ICs and discrete logic. The MultiVolt I/O interfaces directly with 1.0V to 3.3V rails without level shifters. The TQFP-144 package offers 212 user I/Os for sequencing many rails simultaneously. Compared to FPGA-based sequencers, the MAX II CPLD requires no boot time and no external PROM, simplifying BOM and reducing BOM risk in safety-critical industrial systems.
おすすめ
LED Display Drivers & Scan Matrix Control
The EPM570T144C4N drives large LED dot-matrix displays, seven-segment panels, and signage arrays by handling row/column scanning, PWM dimming, and refresh-rate generation in a single device. Its 247.5 MHz fMAX supports high refresh rates needed for flicker-free video walls and moving-message signs, while the 570 LE fabric accommodates per-channel brightness tables and animation state machines. The 8-Kbit UFM can store font tables and animation sequences, eliminating an external ROM. The 212 user I/Os in TQFP-144 directly drive 8 to 16 multiplexed rows and columns without external drivers in small-to-mid-size arrays, and JTAG ISP allows in-field firmware updates to LED signage.
おすすめ
JTAG-Based Board Test Infrastructure (ICT/BIST)
The EPM570T144C4N integrates seamlessly into JTAG-based in-circuit test (ICT) and boundary-scan test (BST) infrastructure via its IEEE 1149.1 compliant TAP controller. Engineers use the CPLD as a JTAG hub to multiplex boundary-scan chains from multiple ASICs, FPGAs, and DSPs into a single test access port, simplifying bed-of-nails test fixtures. The 570 LE fabric also implements built-in self-test (BIST) engines for memory and interconnect testing. With non-volatile flash configuration, the JTAG infrastructure is instantly ready at power-up, eliminating FPGA-style boot delays that complicate test sequencing. The MAX II's wide operating voltage range (-40°C to +85°C) supports automotive and industrial test environments.
おすすめ
Industrial PLC & Motor Control Logic
The EPM570T144C4N delivers deterministic, real-time logic for industrial PLCs, servo drives, and stepper motor controllers where instant-on response and noise immunity are critical. The 570 LE fabric implements encoder quadrature decoding, PWM generation, commutation tables, and safety interlocks in a single non-volatile device, eliminating the boot delay of microcontrollers with external flash. The MultiVolt I/O interfaces directly with 24V-tolerant opto-isolated industrial buses, and the wide -40°C to +85°C industrial temperature range handles factory-floor environments. The 247.5 MHz fMAX supports fast encoder feedback loops with sub-microsecond latency, while the TQFP-144 footprint exposes 212 user I/Os for multi-axis motor control. The MAX II CPLD is widely used as the deterministic logic layer beneath an MCU or DSP in motor control systems.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM570T144C4N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM570T144C4 | EPM570GT144C4N | EPM570T144C5N | EPM570T144A5N | EPM570T144C3N |
|---|---|---|---|---|---|---|
| Package | TQFP-144 (22x22 mm, 0.5 mm pitch) | TQFP-144 (22x22 mm, 0.5 mm pitch) - same | TQFP-144 (22x22 mm, 0.5 mm pitch) - same | TQFP-144 (22x22 mm, 0.5 mm pitch) - same | TQFP-144 (22x22 mm, 0.5 mm pitch) - same | TQFP-144 (22x22 mm, 0.5 mm pitch) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 |
| Equivalent Macrocells | 440 | 440 | 440 | 440 | 440 | 440 |
| Speed Grade (tPD) | C4 (~5.4 ns pin-to-pin) | C4 (~5.4 ns) | C4 (~5.4 ns) | C5 (~4.5 ns, faster) | A5 (automotive temp) | C3 (~7 ns, slower) |
| Family Variant | MAX II (standard) | MAX II | MAX II G (green, lower static power) | MAX II | MAX II (automotive) | MAX II |
| Operating Temperature | -40C to +85C (industrial) | 0C to +85C (commercial, non-N) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +125C (automotive, extended) | -40C to +85C (industrial) |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits |
| Programming Interface | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP |
主な差別化要因
- 570 logic elements vs EPM240's 240 LEs - 2.4x capacity （vs EPM240T100C5N)
- Industrial -40C to +85C temperature range （vs EPM570T144C4 (commercial, non-N))
- TQFP-144 with 212 user I/Os vs TQFP-100's 76 user I/Os （vs EPM570T100C4N)
設計ノート
Decouple every VCCINT and VCCIO pin with a 0.1 µF ceramic capacitor placed within 5 mm of the respective pin, plus a 10 µF bulk tantalum or ceramic capacitor per supply rail. The MAX II datasheet recommends one bulk capacitor per VCCIO bank. Tie all VCCINT pins to a single 2.5 V or 3.3 V rail; do not mix core voltages. Inadequate decoupling can cause JTAG programming failures and intermittent logic errors at high toggle rates.
Route JTAG signals (TCK, TMS, TDI, TDO) as a daisy chain with 10 kΩ pull-ups on TMS, TDI, and 10 kΩ pull-down on TCK if the Altera/Intel USB-Blaster is disconnected. Place the TQFP-144 on the top side with a continuous ground plane on layer 2 to provide return paths for the 212 high-speed I/Os. The 0.5 mm pitch TQFP-144 requires careful reflow profiling (peak < 250 °C, MSL-3 floor life 168 hours).
Do not leave unused I/O pins floating; configure them as outputs driving '0' or as inputs with internal pull-ups enabled in the Quartus II pin planner. Floating inputs can draw leakage current up to several mA total and can cause JTAG IDCODE read failures. Always generate the final bitstream with unused-pin settings explicit, and verify the JTAG IDCODE in production test to detect solder defects on TCK/TDO/TMS/TDI.
コンプライアンス情報
RoHS compliant and lead-free per Altera/Intel material declaration. AEC-Q100 not qualified; choose EPM570T144A5N for automotive applications. Halogen-free status not explicitly stated in provided web data.
