EPM7096LC84-15 vs EPM7128ELC84-12 比較
詳細な並列比較: EPM7096LC84-15 メーカー: Altera および EPM7128ELC84-12 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM7096LC84-15 | EPM7128ELC84-12 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.85 | $10.40 |
| Family | MAX 7000 | MAX 7000 (MAX 7000E series) |
| Series | MAX 7000 (second-generation MAX architecture) | — |
| Macro Cells | 96 | — |
| Logic Array Blocks (LABs) | 4 | 8 |
| Usable Gates | 1,800 | 2,500 |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 76.9 MHz | — |
| User I/O Pins | 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Programmable Type | EE PLD (in-system programmable via JTAG) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG | JTAG (IEEE 1149.1) / ISP |
| 動作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| パッケージ / ケース | 84-PLCC (J-Lead) | — |
| Supplier Device Package | 84-PLCC (29.31 x 29.31 mm) | — |
| 実装タイプ | Surface Mount | Surface Mount (PLCC socket compatible) |
| Data Retention | [DATA_NEEDED: data retention years] | — |
| Erase/Program Endurance | [DATA_NEEDED: erase/program cycle count] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | Non-compliant (legacy 5V part, SnPb finish) |
| Logic Family | — | CMOS, EEPROM-based |
| Macrocells | — | 128 |
| User I/Os | — | 84 |
| Propagation Delay (tpd1) | — | 12 ns |
| Internal Global Clock Frequency | — | 90.9 MHz |
| Setup Time | — | 4.5 ns |
| Supply Voltage (VCCINT / VCCIO) | — | 5 V (4.75 V to 5.25 V) |
| パッケージ | — | 84-pin PLCC (J-Lead, QCCJ) |
| ピン数 | — | 84 |