EPM7096LC84-7 vs EPM7096LC84-15 比較
詳細な並列比較: EPM7096LC84-7 メーカー: Intel および EPM7096LC84-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM7096LC84-7 | EPM7096LC84-15 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $19.85 | $9.85 |
| Family | MAX 7000 | MAX 7000 |
| Macrocells | 96 | — |
| Logic Array Blocks (LABs) | 4 | 4 |
| User I/O Pins | 64 | 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) |
| Speed Grade (tPD) | 7.5 ns | — |
| パッケージ | 84-pin PLCC (Plastic Leaded Chip Carrier) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| 電源電圧 | 5.0 V | — |
| Programming Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Architecture | Second-generation MAX | — |
| I/O Logic Levels | 5.0 V TTL/CMOS-compatible | — |
| 動作温度 | 0C to +70C (commercial, LC suffix) | 0C to +70C (commercial) |
| RoHS ステータス | Non-compliant (original Altera product, leaded PLCC package) | [DATA_NEEDED: RoHS compliance status] |
| ライフサイクル状態 | Obsolete - PCN/PDN issued by Intel | — |
| Series | — | MAX 7000 (second-generation MAX architecture) |
| Macro Cells | — | 96 |
| Usable Gates | — | 1,800 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programmable Type | — | EE PLD (in-system programmable via JTAG) |
| Programming Interface | — | IEEE Std. 1149.1 JTAG |
| パッケージ / ケース | — | 84-PLCC (J-Lead) |
| Supplier Device Package | — | 84-PLCC (29.31 x 29.31 mm) |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Erase/Program Endurance | — | [DATA_NEEDED: erase/program cycle count] |