EPM7160STI100-10 vs EPM7160EQC100-20 比較
詳細な並列比較: EPM7160STI100-10 メーカー: Altera および EPM7160EQC100-20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM7160STI100-10 | EPM7160EQC100-20 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $90.43 | $17.10 |
| Family | MAX 7000S | MAX 7000 CPLD |
| Macrocells | 160 | 160 |
| Usable Gates | 3,200 | 3,200 |
| User I/Os | 84 | — |
| Logic Elements / Blocks | 16 Logic Array Blocks (LABs) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Internal Supply Voltage | 4.75 V to 5.25 V | — |
| I/O Supply Voltage | 5.0 V | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| 動作温度 | -40 C to +85 C (Industrial) | 0 °C to +90 °C (commercial) |
| パッケージ | TQFP-100 (100-pin Thin Quad Flat Pack) | 100-pin Plastic Quad Flat Pack (PQFP, EQFP, EQC100) |
| 実装タイプ | Surface Mount | Surface Mount |
| JTAG / Boundary Scan | IEEE Std. 1149.1 compliant | — |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (for -10 speed grade) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status - not explicitly stated in provided data] | Not RoHS compliant (legacy Altera MAX 7000) |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Series | — | MAX 7000 |
| Architecture | — | CMOS EEPROM-based, non-volatile |
| Logic Array Blocks (LABs) | — | 10 |
| Maximum User I/Os | — | 84 |
| Pin-to-Pin Propagation Delay (tPD) | — | 20 ns |
| Maximum Internal Frequency (fCNT) | — | 62.5 MHz |
| Supply Voltage (VCCINT) | — | 5 V nominal (4.75 V to 5.25 V) |
| I/O Voltage Support | — | 3.3 V or 5 V configurable |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG, 4-pin) |
| Reprogram Cycles (typical) | — | 100 |
| Logic Elements per Macrocell | — | 36 product terms (expandable) |