EPM7160STI100-10 vs EPM7160EQC100-20 对比

详细并排对比 EPM7160STI100-10 出自 Altera 和 EPM7160EQC100-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7160EQC100-20 EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP

EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP

EPM7160EQC100-20 ⚠ 最后一次采购

规格对比

参数 EPM7160STI100-10 EPM7160EQC100-20
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $90.43 $17.10
Family MAX 7000S MAX 7000 CPLD
Macrocells 160 160
Usable Gates 3,200 3,200
User I/Os 84 —
Logic Elements / Blocks 16 Logic Array Blocks (LABs) —
Propagation Delay (tPD) 10 ns —
Maximum Operating Frequency 100 MHz —
Internal Supply Voltage 4.75 V to 5.25 V —
I/O Supply Voltage 5.0 V —
Programmable Type In-System Programmable (EEPROM) —
工作温度 -40 C to +85 C (Industrial) 0 °C to +90 °C (commercial)
封装 TQFP-100 (100-pin Thin Quad Flat Pack) 100-pin Plastic Quad Flat Pack (PQFP, EQFP, EQC100)
安装类型 Surface Mount Surface Mount
JTAG / Boundary Scan IEEE Std. 1149.1 compliant —
PCI Compliance PCI Local Bus Specification Rev. 2.2 (for -10 speed grade) —
RoHS 状态 [DATA_NEEDED: RoHS status - not explicitly stated in provided data] Not RoHS compliant (legacy Altera MAX 7000)
MSL 等级 [DATA_NEEDED: MSL rating] —
Lead-Free [DATA_NEEDED: lead-free status] —
Series — MAX 7000
Architecture — CMOS EEPROM-based, non-volatile
Logic Array Blocks (LABs) — 10
Maximum User I/Os — 84
Pin-to-Pin Propagation Delay (tPD) — 20 ns
Maximum Internal Frequency (fCNT) — 62.5 MHz
Supply Voltage (VCCINT) — 5 V nominal (4.75 V to 5.25 V)
I/O Voltage Support — 3.3 V or 5 V configurable
In-System Programmability — Yes (IEEE 1149.1 JTAG, 4-pin)
Reprogram Cycles (typical) — 100
Logic Elements per Macrocell — 36 product terms (expandable)

数据手册与资源

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