EPM7160STI100-10 vs EPM7160STC100-10 比較
詳細な並列比較: EPM7160STI100-10 メーカー: Altera および EPM7160STC100-10 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EPM7160STC100-10 - MAX 7000S CPLD, 160 Macrocells, 100-pin TQFP | Intel
EPM7160STC100-10 ⚠ ラストタイムバイ仕様比較
| パラメータ | EPM7160STI100-10 | EPM7160STC100-10 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $90.43 | $15.90 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | — |
| Usable Gates | 3,200 | 3,200 |
| User I/Os | 84 | 84 |
| Logic Elements / Blocks | 16 Logic Array Blocks (LABs) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Internal Supply Voltage | 4.75 V to 5.25 V | — |
| I/O Supply Voltage | 5.0 V | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| 動作温度 | -40 C to +85 C (Industrial) | 0 C to +70 C (commercial) |
| パッケージ | TQFP-100 (100-pin Thin Quad Flat Pack) | 100-pin TQFP |
| 実装タイプ | Surface Mount | Surface Mount |
| JTAG / Boundary Scan | IEEE Std. 1149.1 compliant | — |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (for -10 speed grade) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status - not explicitly stated in provided data] | Non-RoHS (legacy Altera part; -10N variant is RoHS) |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 160 |
| Logic Elements | — | 160 macrocells / 10 Logic Array Blocks |
| Supply Voltage (VCC) | — | 5.0 V (4.75 V - 5.25 V) |
| Propagation Delay (tPD1) | — | 10 ns |
| Global Clock Setup Time | — | 6 ns |
| Internal Counter Frequency | — | 100 MHz |
| Technology | — | CMOS, EEPROM-based |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |