EPM7256AEQC208-5N vs EPM7256AETC100-10N 比較
詳細な並列比較: EPM7256AEQC208-5N メーカー: Altera および EPM7256AETC100-10N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM7256AETC100-10N - 256-Macro MAX 7000A CPLD, 10ns, TQFP-100 | Intel (Altera)
EPM7256AETC100-10N Obsolete仕様比較
| パラメータ | EPM7256AEQC208-5N | EPM7256AETC100-10N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $11.50 | $13.10 |
| Family | MAX 7000A | MAX 7000A |
| Logic Family / Base Technology | CMOS, EEPROM-based | — |
| Usable Gates | 5,000 | 5,000 |
| Macrocells | 256 | — |
| User I/Os | 164 | — |
| Dedicated Inputs | 16 | 4 (global clock / clear / OE) |
| ピン数 | 208 | — |
| パッケージ | 208-pin PQFP (Plastic Quad Flat Pack) | 100-pin TQFP |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Maximum Internal Frequency | 172.4 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 5.5 ns | — |
| Speed Grade | -5 | — |
| 動作温度 | 0 C to +70 C (Commercial) | — |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | — |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | unknown | [DATA_NEEDED: not confirmed in provided data] |
| MSLレベル | [DATA_NEEDED: MSL Level] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 256 |
| Maximum User I/Os | — | 84 |
| Logic Elements / LABs | — | 16 Logic Array Blocks |
| Pin-to-Pin Logic Delay | — | 10 ns |
| Maximum Operating Frequency | — | 125 MHz |
| Supply Voltage (Core) | — | 3.3 V |
| MultiVolt I/O Support | — | 2.5 V / 3.3 V / 5.0 V |
| Programmability | — | EEPROM, in-system via JTAG (IEEE 1149.1) |
| 動作温度範囲 | — | 0C to +70C (commercial) [DATA_NEEDED: explicit grade from datasheet] |
| Process Technology | — | 0.30 µm EEPROM |
| Lead-Free / Pb-Free | — | [DATA_NEEDED: not confirmed in provided data] |