EPM7256BQC208-7 vs EPM7256AQC208-7 比較
詳細な並列比較: EPM7256BQC208-7 メーカー: Intel および EPM7256AQC208-7 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM7256BQC208-7 | EPM7256AQC208-7 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.75 | $27.20 |
| Family | MAX 7000B | MAX 7000A |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Usable Gates | 5,000 | 5,000 |
| Macro Cells | 256 | — |
| User I/Os | 164 | — |
| Logic Elements / LABs | 16 Logic Array Blocks | — |
| Maximum Internal Frequency | 126.6 MHz | — |
| Propagation Delay (tPD) | 7.5 ns (-7 speed grade) | — |
| Core Supply Voltage | 2.5 V | — |
| 動作温度 | 0C to +90C (commercial) | — |
| パッケージ | 208-pin PQFP | 208-Pin PQFP (28 x 28 mm) |
| 実装タイプ | Surface Mount | Surface Mount |
| Configuration Memory | Non-volatile EEPROM | EEPROM (non-volatile) |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| In-System Programmability | Yes (via JTAG) | — |
| RoHS ステータス | Compliant per distributor listings | [DATA_NEEDED: RoHS status] |
| Programmable Type | — | In System Programmable (ISP), EEPROM-based |
| Macrocells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 164 |
| Pin-to-Pin Logic Delay (tPD) | — | 7 ns |
| Maximum Counter Frequency | — | 125 MHz |
| Internal Toggle Frequency | — | 227.3 MHz |
| Supply Voltage - Internal | — | 3.0 V to 3.6 V |
| I/O Voltage Compatibility | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) |
| Supplier Device Package | — | 208-PQFP (28x28) |
| 動作温度範囲 | — | 0C to +70C (commercial) |
| JTAG Interface | — | IEEE 1149.1 (JTAG) boundary scan |
| Speed Grade | — | -7 |
| MSLレベル | — | [DATA_NEEDED: MSL level] |