EPM7256BQC208-7 vs EPM7256AQC208-7 对比
详细并排对比 EPM7256BQC208-7 出自 Intel 和 EPM7256AQC208-7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM7256BQC208-7 | EPM7256AQC208-7 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.75 | $27.20 |
| Family | MAX 7000B | MAX 7000A |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Usable Gates | 5,000 | 5,000 |
| Macro Cells | 256 | — |
| User I/Os | 164 | — |
| Logic Elements / LABs | 16 Logic Array Blocks | — |
| Maximum Internal Frequency | 126.6 MHz | — |
| Propagation Delay (tPD) | 7.5 ns (-7 speed grade) | — |
| Core Supply Voltage | 2.5 V | — |
| 工作温度 | 0C to +90C (commercial) | — |
| 封装 | 208-pin PQFP | 208-Pin PQFP (28 x 28 mm) |
| 安装类型 | Surface Mount | Surface Mount |
| Configuration Memory | Non-volatile EEPROM | EEPROM (non-volatile) |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| In-System Programmability | Yes (via JTAG) | — |
| RoHS 状态 | Compliant per distributor listings | [DATA_NEEDED: RoHS status] |
| Programmable Type | — | In System Programmable (ISP), EEPROM-based |
| Macrocells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 164 |
| Pin-to-Pin Logic Delay (tPD) | — | 7 ns |
| Maximum Counter Frequency | — | 125 MHz |
| Internal Toggle Frequency | — | 227.3 MHz |
| Supply Voltage - Internal | — | 3.0 V to 3.6 V |
| I/O Voltage Compatibility | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) |
| Supplier Device Package | — | 208-PQFP (28x28) |
| 工作温度范围 | — | 0C to +70C (commercial) |
| JTAG Interface | — | IEEE 1149.1 (JTAG) boundary scan |
| Speed Grade | — | -7 |
| MSL 等级 | — | [DATA_NEEDED: MSL level] |