EPM7256SQC208-7N vs EPM7256SQI208-10 比較
詳細な並列比較: EPM7256SQC208-7N メーカー: Altera および EPM7256SQI208-10 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM7256SQC208-7N | EPM7256SQI208-10 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $27.20 | $0.40 |
| Family | MAX 7000S | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | 5000 |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 164 | — |
| Speed Grade | -7 (7.5 ns pin-to-pin) | — |
| Maximum Frequency | 128.2 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS EEPROM | CMOS EEPROM |
| Configuration Memory | Non-volatile EEPROM (no external config needed) | EEPROM (non-volatile) |
| パッケージ | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin PQFP (QFP208) |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | Commercial (0C to +70C) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan (ISP capable) | — |
| Minimum DC Input Voltage | -0.5 V | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns | — |
| RoHS ステータス | Compliant (N suffix = lead-free) | [DATA_NEEDED: RoHS status] |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Open-Drain Output | Optional per I/O pin | — |
| Device Family | — | MAX 7000 (EPM7256) |
| Logic Array Blocks | — | 16 |
| Maximum User I/O Pins | — | 164 |
| Propagation Delay (tPD) | — | 10 ns |
| Supply Voltage Range | — | 4.5 V to 5.5 V |
| In-System Programmable | — | Yes (IEEE 1149.1 JTAG) |
| Package Body Material | — | Plastic/Epoxy |
| Terminal Form | — | Gull Wing |
| 動作温度範囲 | — | -40 C to +85 C (Industrial) |
| JESD-30 Package Code | — | S-PQFP-G208 |
| JESD-609 Terminal Finish Code | — | E3 |