EPM9320GC280-15 vs EPM9320BC356-15 比較
詳細な並列比較: EPM9320GC280-15 メーカー: Altera および EPM9320BC356-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
EPM9320GC280-15 Obsolete仕様比較
| パラメータ | EPM9320GC280-15 | EPM9320BC356-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $92.50 | $31.20 |
| Family | MAX 9000 (EPM9320) | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based, Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) - third generation |
| Usable Gates | 6,000 | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 (16 macrocells per LAB) | — |
| Pin-to-Pin Propagation Delay | 15 ns | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Maximum User I/O Pins | 164 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5.0 V typical) |
| I/O Voltage Levels | 3.3 V or 5 V (configurable) | — |
| Programmability | 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG | — |
| パッケージ | 280-pin Ceramic Pin Grid Array (CPGA-280) | 356-ball LBGA (BGA-356, 35x35 mm) |
| 実装タイプ | Through-hole (PGA socket) | Surface Mount |
| 動作温度 | 0 C to +70 C (commercial) | — |
| MSLレベル | 3 (168 hours) | — |
| RoHS ステータス | ROHS3 compliant (per fpgalink listing) | [DATA_NEEDED: RoHS compliance status] |
| Technology Node | CMOS EEPROM, third-generation MAX | — |
| Pin-to-Pin Delay (max) | — | 15 ns |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (5.0-V ISP via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| Programmable Type | — | In System Programmable |
| Operating Temperature Grade | — | Commercial |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |