EPM9320GC280-15 vs EPM9320BC356-15 Comparison

Detailed side-by-side comparison of EPM9320GC280-15 by Altera and EPM9320BC356-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320GC280-15 EPM9320BC356-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $92.50 $31.20
Family MAX 9000 (EPM9320) MAX 9000
Device Type CPLD - Complex Programmable Logic Device CPLD (Complex Programmable Logic Device)
Architecture CMOS EEPROM-based, Multiple Array MatriX (MAX) Multiple Array MatriX (MAX) - third generation
Usable Gates 6,000 β€”
Macrocells 320 320
Logic Array Blocks (LABs) 20 (16 macrocells per LAB) β€”
Pin-to-Pin Propagation Delay 15 ns β€”
Maximum Internal Frequency 117.6 MHz β€”
Maximum User I/O Pins 164 β€”
Supply Voltage (VCC) 4.75 V to 5.25 V 4.75 V to 5.25 V (5.0 V typical)
I/O Voltage Levels 3.3 V or 5 V (configurable) β€”
Programmability 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG β€”
Package 280-pin Ceramic Pin Grid Array (CPGA-280) 356-ball LBGA (BGA-356, 35x35 mm)
Mounting Type Through-hole (PGA socket) Surface Mount
Operating Temperature 0 C to +70 C (commercial) β€”
MSL Level 3 (168 hours) β€”
RoHS Status ROHS3 compliant (per fpgalink listing) [DATA_NEEDED: RoHS compliance status]
Technology Node CMOS EEPROM, third-generation MAX β€”
Pin-to-Pin Delay (max) β€” 15 ns
Process Technology β€” CMOS EEPROM
In-System Programmability β€” Yes (5.0-V ISP via JTAG)
JTAG Interface β€” IEEE Std. 1149.1 compliant
Programmable Type β€” In System Programmable
Operating Temperature Grade β€” Commercial
Lead-Free β€” [DATA_NEEDED: lead-free status]

Datasheets & Resources

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