EPM9320LC84-15 vs EPM9320LI84-20 比較
詳細な並列比較: EPM9320LC84-15 メーカー: Intel および EPM9320LI84-20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9320LC84-15 | EPM9320LI84-20 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $17.95 | $12.80 |
| Family | MAX 9000 | MAX 9000 |
| Series | EPM9320 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | — |
| Logic Array Blocks (LABs) | 20 | — |
| Propagation Delay (tPD) | 15 ns (max) | 20 ns |
| 最大クロック周波数 | 117.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | — |
| パッケージ | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-PLCC (J-Lead, plastic LCC) |
| 実装タイプ | Surface Mount | Surface Mount (PLCC socket-compatible) |
| 動作温度 | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | -40 C to +85 C (industrial) |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | — |
| Built-in Pull-up Resistors | Yes, on every I/O pin | — |
| Architecture Feature | Pin-locking across design iterations | — |
| RoHS ステータス | [DATA_NEEDED: confirm from manufacturer] | [DATA_NEEDED: RoHS compliance] |
| Manufacturer | — | Altera (acquired by Intel) |
| User I/Os | — | 60 |
| Internal Frequency | — | 118 MHz |
| 電源電圧 | — | 5.0 V |
| Logic Family | — | CMOS, EEPROM-based |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Process Technology | — | High-performance CMOS EEPROM |