EPM9320RC208-15 vs EPM9320RI208-20C 比較
詳細な並列比較: EPM9320RC208-15 メーカー: Altera および EPM9320RI208-20C メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9320RI208-20C - 320-Macrocell MAX 9000 CPLD, 5V, 208-RQFP | Intel
EPM9320RI208-20C Obsolete仕様比較
| パラメータ | EPM9320RC208-15 | EPM9320RI208-20C |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $22.10 |
| Device Family | MAX 9000 | — |
| Macro Cells | 320 | — |
| Usable Gates | 6,000 | 6,000 |
| Pin-to-Pin Propagation Delay | 15 ns (speed grade -15) | — |
| 最大クロック周波数 | 117.6 MHz | — |
| 電源電圧 | 5.0 V | — |
| Configuration Technology | EEPROM-based (non-volatile) | — |
| In-System Programmability | Yes (ISP via JTAG) | Yes (5.0 V ISP via JTAG) |
| JTAG Interface | IEEE Std. 1149.1 | — |
| パッケージ | 208-pin RQFP (Power QFP) | 208-pin RQFP (Plastic Quad Flat Pack) |
| Package Type | 208-BFQFP Exposed Pad | — |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | [DATA_NEEDED: operating temperature range] | — |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Logic Array Blocks | [DATA_NEEDED: LAB count] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | — |
| ライフサイクル状態 | Obsolete (PDN0706, 2007) | — |
| Family | — | MAX 9000 |
| Device Type | — | EE PLD / CPLD |
| Logic Elements / Macrocells | — | 320 |
| Number of Flip-Flops | — | 484 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum Internal Clock Frequency | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 20 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V or 5.0 V |
| Programmable Interface | — | JTAG (IEEE Std. 1149.1) BST |
| Technology | — | CMOS EEPROM |
| Operating Temperature (Industrial) | — | -40C to +85C |
| Lead-Free / RoHS | — | Information not confirmed from verified data [DATA_NEEDED: RoHS status] |