EPM9560GC280-15 vs EPM9560ARI240-10 比較
詳細な並列比較: EPM9560GC280-15 メーカー: Altera および EPM9560ARI240-10 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 Obsolete仕様比較
| パラメータ | EPM9560GC280-15 | EPM9560ARI240-10 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $115.00 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (CMOS EEPROM-based CPLD) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 560 | 560 |
| Typical Gates | 12,000 | — |
| Maximum Operating Frequency | 117.6 MHz | — |
| Propagation Delay (tpd) | 15 ns (speed grade -15) | — |
| Propagation Delay (alternate datasheet figure) | 16.6 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Package Type | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | — |
| 実装タイプ | Through-Hole | Surface Mount |
| Programmability | In-System Programmable (ISP) via JTAG IEEE 1149.1 | — |
| Technology | CMOS EEPROM, 0.5 um process (MAX third-gen) | CMOS, EEPROM-based configuration |
| Architecture | Multiple Array MatriX (MAX) | — |
| RoHS ステータス | Non-compliant (ceramic CPGA, contains lead) | [DATA_NEEDED: RoHS status] |
| ライフサイクル状態 | Obsolete (legacy Altera MAX 9000 family) | — |
| Usable Gates | — | 12,000 |
| User I/O Pins | — | 191 |
| パッケージ | — | 240-pin RQFP (PowerQuad Flat Pack) |
| Pin-to-Pin Propagation Delay | — | 10 ns |
| Internal Frequency | — | 144.9 MHz |
| 電源電圧 | — | 5.0 V |
| 動作温度範囲 | — | -40 C to +85 C (industrial) |
| Configuration Memory | — | EEPROM (non-volatile, instant-on) |
| Logic Architecture | — | Multiple Array MatriX (MAX) with global interconnect array |
| Moisture Sensitivity Level | — | [DATA_NEEDED: MSL level] |
| Number of Terminals | — | 240 |
| Terminal Form | — | Gull Wing |