EPM9560RC-15 vs EPM9480RC240-15 比較
詳細な並列比較: EPM9560RC-15 メーカー: Altera および EPM9480RC240-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel
EPM9560RC-15 ⚠ ラストタイムバイ仕様比較
| パラメータ | EPM9560RC-15 | EPM9480RC240-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $30.10 | $91.68 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 (40 macrocells each) | — |
| Maximum User I/O Pins | 191 | — |
| Pin-to-Pin Delay (tPD1) | 15 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| 動作温度 | 0 C to +70 C (commercial) | [DATA_NEEDED: operating temperature range] |
| パッケージ | 240-pin RQFP (32x32 mm) | 240-pin RQFP (32x32 mm) |
| 実装タイプ | Surface Mount | Surface Mount |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| Process Technology | CMOS EEPROM | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | RoHS non-compliant |
| In-System Programmability | Yes (5.0 V ISP via JTAG) | — |
| Programmable Type | — | In System Programmable (ISP) |
| Device Family | — | MAX 9000 |
| Macro Cells | — | 480 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Internal Supply Voltage | — | 4.75 V to 5.25 V |
| Configuration Technology | — | EEPROM-based (non-volatile) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Supplier Device Package | — | 240-RQFP (32x32) |
| Number of I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Lead Free Status | — | [DATA_NEEDED: lead free status] |
| Logic Architecture | — | Multiple Array MatriX (MAX) third-generation |
| Supply Voltage (5.0 V nominal) | — | 5.0 V |