EPM9560RC208-20N vs EPM9560WC208-20 比較
詳細な並列比較: EPM9560RC208-20N メーカー: Intel および EPM9560WC208-20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9560WC208-20 - 560-Macrocell CPLD, 23.6ns, PQFP-208 | Intel/Altera
EPM9560WC208-20 Obsolete仕様比較
| パラメータ | EPM9560RC208-20N | EPM9560WC208-20 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $25.80 |
| Device Family | MAX 9000 (EPM9560) | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | — |
| Propagation Delay (tPD) | 20 ns | — |
| パッケージ | 208-pin RQFP (PowerQuad Flat Pack) | PQFP-208 (RQFP/WQFP) |
| User I/O Pins | 149 | 149 |
| 電源電圧 | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes, JTAG BST (IEEE 1149.1) |
| JTAG Interface | IEEE Std. 1149.1 | — |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) [DATA_NEEDED: exact temp grade] |
| RoHS ステータス | Lead-free (N suffix) | Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc] |
| Logic Architecture | Multiple Array MatriX (MAX), third-generation CMOS EEPROM | — |
| Flip-Flops | 772 (per EPM9560 series data) | — |
| Speed Grade | -20 (20 ns) | — |
| MSLレベル | [DATA_NEEDED: MSL level] | [DATA_NEEDED] |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (EPLD) |
| Logic Array Blocks (LABs) | — | 35 |
| Maximum Propagation Delay (tPD) | — | 23.6 ns |
| Process Technology | — | CMOS, EEPROM-based |
| Supply Voltage (VCCINT) | — | 5 V (typical, see datasheet) |
| I/O Voltage (VCCIO) | — | 3.3 V or 5 V (multi-voltage I/O) |
| Pin/Package Suffix | — | W = power PQFP; -20 = 23.6 ns speed grade |
| Lead-Free | — | [DATA_NEEDED] |
| ハロゲンフリー | — | [DATA_NEEDED] |