EPM9560RC240-1O vs EPM9560RC240-12 比較
詳細な並列比較: EPM9560RC240-1O メーカー: Intel および EPM9560RC240-12 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EPM9560RC240-1O - MAX 9000 CPLD, 560 Macrocells, 216 I/O, RQFP-240 | Altera
EPM9560RC240-1O ⚠ ラストタイムバイ
仕様比較
| パラメータ | EPM9560RC240-1O | EPM9560RC240-12 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $51.07 | $9.95 |
| Family | MAX 9000 | MAX 9000 (EPM9560) |
| Usable Gates | 12,000 | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 20 |
| Maximum User I/O Pins | 216 | — |
| Propagation Delay (tPD) | 12 ns (typ, -1 speed grade) | — |
| Global Setup Time (tFSU) | 3.0 ns | — |
| Clock-to-Output (tFCO) | 4.8 ns | — |
| Maximum Internal Frequency (fCNT) | 145 MHz | — |
| Supply Voltage (VCC) | 5.0 V | — |
| Operating Temperature (Grade) | -40C to +85C (industrial, "-1O" suffix) | — |
| Process Technology | CMOS EEPROM, 0.65 um | CMOS |
| Programming | In-system programmable via IEEE 1149.1 JTAG | — |
| Architecture | Multiple Array MatriX (MAX), third generation | — |
| パッケージ | RQFP-240 (240-pin Reduced-height QFP) | PQFP-240 (RC240) 0.500 mm pitch, gull-wing |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | Compliant (per Altera/Intel product page) | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | Yes | — |
| Device Type | — | EE PLD / CPLD |
| Flip-Flops | — | 772 |
| User I/O Pins | — | 191 |
| Maximum Propagation Delay (tPD) | — | 13.4 ns |
| Speed Grade | — | -12 (13.4 ns tPD) |
| Maximum Operating Frequency (estimated) | — | ~76 MHz registered |
| Core Supply Voltage (VCCINT) | — | 5 V |
| I/O Logic Levels | — | 3.3 V or 5 V (configurable) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Programming Interface | — | IEEE 1149.1 JTAG |
| 動作温度 | — | [DATA_NEEDED: operating temperature grade] |