EPM9560RC240-12 - 560 Macrocell EE PLD, 12ns PQFP-240 | Altera
部品番号: EPM9560RC240-12 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $23.17 | $23.17 |
| 10 | $19.5 | $195.00 |
| 100 | $15.8 | $1,580.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $9.95 | $9,950.00 |
EPM9560RC240-12 概要
A Programmable Logic Device (PLD) is a non-volatile digital integrated circuit whose logic function is defined after manufacture by the end user via an EEPROM or SRAM-based configuration cell matrix. EE PLDs retain their configuration when power is removed, which distinguishes them from SRAM-based FPGAs that require a boot PROM. Within the broader taxonomy, the MAX 9000 family occupies the high-density CPLD (Complex PLD) tier - sitting between simple SPLDs/GALs and full FPGAs - and is engineered for glue-logic integration, bus interfacing, state-machine consolidation, and peripheral decoding in systems where non-volatility and deterministic timing matter more than raw gate count.
Key features of the EPM9560RC240-12 include 12 ns combinatorial tPD, in-system programmability via the IEEE 1149.1 JTAG interface, 191 high-drive I/O pins organized in I/O banks with per-pin slew-rate and pull-up control, and an operating junction temperature range suitable for commercial and industrial environments. The device supports the Altera MAX+PLUS II and Quartus design flows, allowing legacy MAX-series designs to be ported without HDL rewrites.
The MAX 9000 architecture combines a Logic Array Block (LAB) fabric with a programmable interconnect array (PIA), giving uniform propagation delay across all LAB-to-LAB paths. Each macrocell contains a programmable flip-flop with D, T, JK, or SR modes, plus product-term sharing logic, which makes the family efficient for wide combinatorial decoders and registered state machines rather than pipelined datapath work.
Typical applications include peripheral bus decoding in PCI/ISA bridge designs, address decoding for DSP and microcontroller subsystems, register-bank expansion in telecom backplane glue logic, and industrial control PLCs where deterministic timing and non-volatile configuration are required. The wide I/O count also makes the EPM9560 useful for legacy test equipment and instrumentation front ends.
Designers should note that the EPM9560RC240 series is now considered a mature / legacy device family by Altera (now Intel FPGA), with -12, -15, and -20 speed grades typically available on the distributor surplus market rather than as fully production-stocked parts. New designs should consider MAX II or MAX V CPLDs as pin-compatible modern alternatives where possible. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: EPM9560RC240-12 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9560RC240-12 （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Logic Family, RoHS Status, Family.
クイック比較ツール — 並列比較する代替部品を選択:
EPM9560RC240-10N
✅ ドロップイン✓ 在庫あり
$168 / 個
データシートを見る →EPM9560RC240-10
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560ARC240-10
✅ ドロップイン✓ 在庫あり
$28.8 / 個
データシートを見る →EPM9560ARI240-10
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560ARC240-10N
✅ ドロップイン✓ 在庫あり
$19.5 / 個
データシートを見る →EPM9560ARI240-10N
✅ ドロップイン✓ 在庫あり
$105 / 個
データシートを見る →EPM9560RC240-12 最大定格＆電気的特性
| Family | MAX 9000 (EPM9560) |
| Device Type | EE PLD / CPLD |
| Macrocells | 560 |
| Flip-Flops | 772 |
| User I/O Pins | 191 |
| Logic Array Blocks (LABs) | 20 |
| Maximum Propagation Delay (tPD) | 13.4 ns |
| Speed Grade | -12 (13.4 ns tPD) |
| Maximum Operating Frequency (estimated) | ~76 MHz registered |
| Core Supply Voltage (VCCINT) | 5 V |
| I/O Logic Levels | 3.3 V or 5 V (configurable) |
| パッケージ | PQFP-240 (RC240) 0.500 mm pitch, gull-wing |
| 実装タイプ | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) |
| Programming Interface | IEEE 1149.1 JTAG |
| Process Technology | CMOS |
EPM9560RC240-12 pqfp-240 (rc240) 0.500 mm pitch, gull-wing ピン配置ガイド
EPM9560RC240-12 (pqfp-240 (rc240) 0.500 mm pitch, gull-wing パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EPM9560RC240-12.
詳細は データシート をご参照ください。
主な用途
EPM9560RC240-12 の用途: 6 件s: PCI / ISA Bus Address Decoding, DSP Subsystem Glue Logic, Telecom Backplane Control Logic, Industrial PLC I/O Expansion, Legacy Test & Measurement Instrumentation, Aerospace Avionics Databus Interface.
PCI / ISA Bus Address Decoding
The EPM9560RC240-12 is well suited as a centralized address and command decoder for PCI or ISA bridge designs, where its 191 user I/O pins can simultaneously handle 32-bit address plus full command/byte-enable busses for multiple peripherals. With 560 macrocells, complex map decoders with chip-select strobe generation fit easily, and the 13.4 ns tPD comfortably meets 33 MHz PCI timing budgets when pipelined correctly. Place the EPM9560 between the host bridge and peripheral glue logic with its I/O bank at 5V to match legacy peripherals.
おすすめ
DSP Subsystem Glue Logic
In DSP-based designs (e.g. TMS320, ADSP-21xx, or similar), the EPM9560RC240-12 consolidates wait-state generators, bus arbiters, and memory-bank select logic into one non-volatile CPLD, replacing dozens of discrete 74LS/74F glue chips. The 772 flip-flops are ample for registered state machines handling DMA handshakes, while the deterministic 13.4 ns tPD simplifies worst-case timing analysis critical for real-time DSP pipelines. Power it from the same 5V rail as the DSP and configure its I/O bank voltages per peripheral interface standard.
おすすめ
Telecom Backplane Control Logic
Backplane line-card designs in telecom and networking equipment historically rely on the EPM9560RC240-12 for shelf-management glue: alarm scanning, LED driving, EEPROM emulation, and local bus arbitration across 191 I/O lines. The non-volatile EEPROM configuration means shelf controllers start up in a known state without boot PROM - critical for hot-swap redundancy schemes. The 5V core and mixed 3.3V/5V I/O banks let a single EPM9560 straddle legacy and modern backplane voltage domains in one part.
おすすめ
Industrial PLC I/O Expansion
Programmable Logic Controllers (PLCs) benefit from the EPM9560RC240-12's wide I/O count when interfacing to discrete sensors, relay drivers, and encoder inputs - the 191 I/O can absorb an entire 96-point digital I/O module's worth of conditioning and latching logic. Industrial-grade variants (EPM9560ARI240-10) extend the operating temperature range to -40C to +100C suitable for factory-floor enclosures. The deterministic tPD and non-volatile configuration are essential for safety-related PLC logic that must power up in a defined state.
おすすめ
Legacy Test & Measurement Instrumentation
Bench-top instruments (oscilloscopes, logic analyzers, protocol testers) often use the EPM9560RC240-12 for front-panel keyboard scanning, display multiplexing, and timing/sequencer logic because its 560 macrocells can replace several PAL/GAL devices with a single non-volatile part. The 5V I/O tolerance matches legacy TTL front-end ICs, while mixed 3.3V banks can interface newer ADC/DAC interfaces. Engineers repairing vintage equipment rely on this part for exact form-fit-function replacement.
おすすめ
Aerospace Avionics Databus Interface
Avionics MIL-STD-1553 and ARINC 429 databus interfaces require deterministic, low-latency glue logic between transceivers and host CPUs - exactly the use case where the EPM9560RC240-12's uniform 13.4 ns tPD and non-volatile configuration shine. The 191 I/O pins can handle full 16-bit databus plus discrete avionics discretes in a single CPLD, while 5V core and I/O tolerance matches legacy avionic bus drivers. Industrial/extended temp variants (EPM9560ARI240-10) are preferred for cockpit thermal environments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9560RC240-12 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9560RC240-10N | EPM9560RC240-10 | EPM9560ARC240-10 | EPM9560ARI240-10 | EPM9560ARC240-10N | EPM9560ARI240-10N |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PQFP-240 (RC240) | PQFP-240 (RC240) | PQFP-240 (RC240) | PQFP-240 (RC240) | PQFP-240 (RC240) | PQFP-240 (RC240) | PQFP-240 (RC240) |
| Family / Revision | MAX 9000 (original) | MAX 9000 (original) | MAX 9000 (original) | MAX 9000A | MAX 9000A | MAX 9000A | MAX 9000A |
| Speed Grade (tPD) | 13.4 ns (-12) | 10 ns (-10) | 10 ns (-10) | 10 ns (-10) | 10 ns (-10) | 10 ns (-10) | 10 ns (-10) |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 | 560 |
| Flip-Flops | 772 | 772 | 772 | 772 | 772 | 772 | 772 |
| User I/O | 191 | 191 | 191 | 191 | 191 | 191 | 191 |
| Core Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
主な差別化要因
- Drop-in PQFP-240 alternatives are all same-brand Altera MAX 9000 （vs EPM9560RC240-10N)
- MAX 9000A revision provides improved I/O and lower dynamic power （vs EPM9560ARC240-10)
- Industrial temperature grade available without PCB change （vs EPM9560ARI240-10)
設計ノート
The EPM9560RC240-12 requires a clean 5V VCCINT supply with at least 100 uF of bulk decoupling distributed across the PQFP-240 footprint, plus 0.1 uF ceramic bypass capacitors on every VCC/GND pair (typically placed within 5 mm of the device). Each VCCIO bank should have its own decoupling; the datasheet specifies four I/O banks each requiring independent filtering. Power sequencing is not critical because the EEPROM configuration is non-volatile, but ensure VCC ramps monotonically to avoid latch-up.
The PQFP-240 package uses 0.500 mm pitch gull-wing leads, which is at the wide end of modern SMT capability but easily handled with standard reflow profiles. Recommended land pattern is per IPC-7351 PQFP-0.5; keep-out zones under the package allow via-in-pad thermal relief to a full ground plane. Route JTAG signals (TCK, TMS, TDI, TDO) with 50 ohm controlled impedance if the JTAG chain exceeds 50 mm to avoid programming failures.
Estimated: I/O bank voltage (VCCIO) must match the logic level of the connected peripheral - mixing 3.3V and 5V peripherals in the same bank will damage lower-voltage parts. Do not leave unused I/O pins floating; configure them as outputs driving low or as inputs with internal pull-ups enabled, otherwise the EEPROM-configured I/O may oscillate during power-up and inject noise into VCCIO. Verify the speed-grade ordering code carefully: -12 = 13.4 ns tPD, -15 = 18 ns tPD, -10 = 10 ns tPD, and -7 = 7.5 ns tPD.
コンプライアンス情報
RoHS, lead-free, REACH status are not explicitly documented for the EPM9560RC240-12 in the verified web data. AEC-Q100 not applicable for legacy industrial/automotive-use MAX 9000 CPLD family.
