EPM9560RC304-15F vs EPM9560RI304-15 比較
詳細な並列比較: EPM9560RC304-15F メーカー: Altera および EPM9560RI304-15 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F Obsolete仕様比較
| パラメータ | EPM9560RC304-15F | EPM9560RI304-15 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $18.75 | $112.00 |
| Device Family | MAX 9000 | MAX 9000 |
| Series | EPM9560 | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | — |
| Propagation Delay (tpd) | 16.6 ns (max) | 11.4 ns (per digchip datasheet); 16.6 ns reported by MicrochipUSA |
| Maximum Internal Frequency | 117.6 MHz | 145 MHz |
| Core Supply Voltage | 5.0 V | — |
| User I/O Pins | 212 | — |
| Dedicated Inputs | 4 | 4 |
| Logic Array Blocks (LABs) | 16 (40 macrocells each) | — |
| パッケージ | RQFP-304 (304-pin Plastic QFP) | — |
| Programming Technology | 5.0 V in-system EEPROM via JTAG (IEEE 1149.1) | — |
| Architecture | Multiple Array MatriX (MAX) with PIA interconnect | Multiple Array MatriX (MAX) - EEPROM-based CPLD |
| Boundary Scan Test (BST) | Yes, JTAG-compliant | — |
| 動作温度 | -40C to +85C (industrial) | 0 C to 70 C (commercial) |
| Process Technology | High-performance CMOS, EEPROM-based | 0.5 µm CMOS EEPROM |
| 実装タイプ | Surface Mount | Surface Mount |
| MSLレベル | 3 (168 hours) | — |
| RoHS ステータス | [DATA_NEEDED: rohs status - not stated in source] | [DATA_NEEDED: RoHS status] |
| Flip-Flops | — | 772 |
| User I/Os | — | 212 (216 per some datasheets) |
| Total Terminals | — | 304 |
| Package Code | — | HFQFP / S-PQFP-G304 |
| Package Type | — | 304-pin RQFP (Quad Flat Pack, gull-wing) |
| Speed Grade | — | -15 |
| Supply Voltage (VCCINT/VCCIO) | — | 4.5 V to 5.5 V (5 V typical) |
| I/O Logic Levels | — | 3.3 V or 5 V configurable |
| Temperature Grade | — | Industrial (per Partstack listings) |
| Logic Family | — | CMOS |
| Programming | — | 5.0-V in-system programmable via JTAG (IEEE 1149.1) |