EPM9560RCRC304-15 vs EPM9560RC304-5 比較
詳細な並列比較: EPM9560RCRC304-15 メーカー: Altera および EPM9560RC304-5 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9560RCRC304-15 | EPM9560RC304-5 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $0.00 |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 (EPM9560) |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Macro Cells | 560 | — |
| Usable Gates | 12,000 | 12,000 |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns | — |
| Maximum Frequency | 117.6 MHz | — |
| 電源電圧 | 5.0 V | 5.0 V |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | — |
| In-System Programmability (ISP) | Yes, via IEEE Std. 1149.1 JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 (built-in) | — |
| パッケージ | 304-pin RQFP (PowerQuad Flat Pack) | 304-pin RQFP (PowerQuad II) |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度範囲 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Number of User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Architecture | Third-generation Multiple Array MatriX (MAX) | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | [DATA_NEEDED: number of LABs] |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Device Type | — | Complex Programmable Logic Device (CPLD) / EPLD |
| Macrocells | — | 560 |
| Maximum Operating Frequency | — | 117.6 MHz (family -15 grade reference) |
| Speed Grade | — | -5 (fastest grade in family) |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG ISP) |
| 湿気感度レベル（MSL） | — | 3 (168 Hours) |
| Manufacturer Standard Lead Time | — | 1-7 Days (distributor listing) |
| Number of I/O Pins | — | [DATA_NEEDED: number of user I/O pins] |
| Propagation Delay (tPD) | — | [DATA_NEEDED: propagation delay] |