EPM9560RCRC304-15 vs EPM9560RI304-15 比較
詳細な並列比較: EPM9560RCRC304-15 メーカー: Altera および EPM9560RI304-15 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9560RCRC304-15 | EPM9560RI304-15 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $112.00 |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Macro Cells | 560 | — |
| Usable Gates | 12,000 | — |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns | — |
| Maximum Frequency | 117.6 MHz | — |
| 電源電圧 | 5.0 V | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | — |
| In-System Programmability (ISP) | Yes, via IEEE Std. 1149.1 JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 (built-in) | — |
| パッケージ | 304-pin RQFP (PowerQuad Flat Pack) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度範囲 | [DATA_NEEDED: operating temperature range] | — |
| Number of User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Architecture | Third-generation Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) - EEPROM-based CPLD |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Macrocells | — | 560 |
| Flip-Flops | — | 772 |
| User I/Os | — | 212 (216 per some datasheets) |
| Dedicated Inputs | — | 4 |
| Total Terminals | — | 304 |
| Package Code | — | HFQFP / S-PQFP-G304 |
| Package Type | — | 304-pin RQFP (Quad Flat Pack, gull-wing) |
| Propagation Delay (tpd) | — | 11.4 ns (per digchip datasheet); 16.6 ns reported by MicrochipUSA |
| Maximum Internal Frequency | — | 145 MHz |
| Speed Grade | — | -15 |
| Supply Voltage (VCCINT/VCCIO) | — | 4.5 V to 5.5 V (5 V typical) |
| I/O Logic Levels | — | 3.3 V or 5 V configurable |
| 動作温度 | — | 0 C to 70 C (commercial) |
| Temperature Grade | — | Industrial (per Partstack listings) |
| Logic Family | — | CMOS |
| Programming | — | 5.0-V in-system programmable via JTAG (IEEE 1149.1) |
| Process Technology | — | 0.5 µm CMOS EEPROM |