EPM9560RCRC304-15 vs EPM9560RI304-15 Comparaison
Comparaison détaillée côte à côte de EPM9560RCRC304-15 par Altera et EPM9560RI304-15 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9560RCRC304-15 | EPM9560RI304-15 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $112,00 |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Macro Cells | 560 | — |
| Usable Gates | 12,000 | — |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns | — |
| Maximum Frequency | 117.6 MHz | — |
| Tension d'alimentation | 5.0 V | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | — |
| In-System Programmability (ISP) | Yes, via IEEE Std. 1149.1 JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 (built-in) | — |
| Boîtier | 304-pin RQFP (PowerQuad Flat Pack) | — |
| Type de montage | Surface Mount | Surface Mount |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Number of User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Architecture | Third-generation Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) - EEPROM-based CPLD |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Macrocells | — | 560 |
| Flip-Flops | — | 772 |
| User I/Os | — | 212 (216 per some datasheets) |
| Dedicated Inputs | — | 4 |
| Total Terminals | — | 304 |
| Package Code | — | HFQFP / S-PQFP-G304 |
| Package Type | — | 304-pin RQFP (Quad Flat Pack, gull-wing) |
| Propagation Delay (tpd) | — | 11.4 ns (per digchip datasheet); 16.6 ns reported by MicrochipUSA |
| Maximum Internal Frequency | — | 145 MHz |
| Speed Grade | — | -15 |
| Supply Voltage (VCCINT/VCCIO) | — | 4.5 V to 5.5 V (5 V typical) |
| I/O Logic Levels | — | 3.3 V or 5 V configurable |
| Température de fonctionnement | — | 0 C to 70 C (commercial) |
| Temperature Grade | — | Industrial (per Partstack listings) |
| Logic Family | — | CMOS |
| Programming | — | 5.0-V in-system programmable via JTAG (IEEE 1149.1) |
| Process Technology | — | 0.5 µm CMOS EEPROM |