LTC2260IUJ-14 vs LTC2257IUJ-14 比較
詳細な並列比較: LTC2260IUJ-14 メーカー: Analog Devices および LTC2257IUJ-14 メーカー: Analog Devices。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Analog Devices
LTC2257IUJ-14 - 14-bit, 40Msps Ultralow Power 1.8V ADC | Analog Devices
LTC2257IUJ-14 ✓ 生産中仕様比較
| パラメータ | LTC2260IUJ-14 | LTC2257IUJ-14 |
|---|---|---|
| ブランド | Analog Devices | Analog Devices |
| カテゴリ | ADC/DAC | ADC/DAC |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $20.95 | $16.40 |
| 分解能 | 14 bit | 14 bit |
| Sample Rate | 105 Msps | 40 Msps |
| Number of Input Channels | 1 | — |
| Architecture | Pipelined | Pipelined |
| Supply Voltage (Analog/Digital) | 1.8 V (single supply) | — |
| Power Consumption | 106 mW at 105 Msps | — |
| INL (typical) | ±1 LSB | ±1 LSB |
| DNL (typical) | ±0.3 LSB | ±0.3 LSB |
| Transition Noise | 1.2 LSB RMS | 1.13 LSB RMS |
| Missing Codes | None over temperature | None over temperature |
| Input Range (selectable) | 1 V P-P to 2 V P-P | — |
| Full-Power Bandwidth | 800 MHz | — |
| Output Modes | CMOS, DDR CMOS, DDR LVDS | — |
| Output Supply Range | 1.2 V to 1.8 V (CMOS) | — |
| Configuration Interface | Serial SPI | SPI serial port |
| Power-Saving Modes | Shutdown, Nap | Shutdown, Nap modes |
| Optional Features | Data output randomizer, clock duty cycle stabilizer | — |
| パッケージ | 40-QFN (6x6 mm) | 40-QFN (UJ) 6x6 mm with exposed pad |
| Pin/Package Compatibility | Pin-compatible with LTC2260-12, LTC2261-14, LTC2259-14 | — |
| 動作温度範囲 | -40 C to +85 C (Industrial, IUJ suffix) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | Compliant (#PBF suffix) | Compliant (#PBF suffix) |
| Number of Inputs | — | 1 |
| Input Type | — | Differential (single-ended capable) |
| Analog Supply Voltage | — | 1.7 V to 1.9 V (1.8 V nominal) |
| Digital Output Supply | — | 1.2 V to 1.8 V |
| Power Dissipation | — | [DATA_NEEDED: exact mW at 40 Msps, datasheet figure] |
| Output Interface | — | CMOS / DDR CMOS / DDR LVDS (selectable) |
| SNR | — | [DATA_NEEDED: SNR dBFS at fin] |
| SFDR | — | [DATA_NEEDED: SFDR dBc at fin] |
| 動作温度 | — | -40C to +85C (I grade) |
| Clock Duty-Cycle Stabilizer | — | Optional, on-chip |
| Reference Type | — | External or internal (per variant) |