LTC2260IUJ-14 - 14-Bit 105Msps Ultralow Power 1.8V ADC | ADI
部品番号: LTC2260IUJ-14 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $33.5 | $33.50 |
| 10 | $30.15 | $301.50 |
| 100 | $26.8 | $2,680.00 |
| 500 | $23.45 | $11,725.00 |
| 1,000 | $20.95 | $20,950.00 |
LTC2260IUJ-14 概要
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous-time analog signals and converts them into discrete digital codes for processing by microcontrollers, DSPs, FPGAs, or software. Within the broader signal chain, the ADC sits between the analog front end (amplifiers, filters, drivers) and the digital back end. Pipelined ADCs like the LTC2260-14 use a multi-stage architecture to achieve high sample rates at moderate resolution while keeping per-stage comparator counts and power dissipation low, making them well suited for high-speed data acquisition, communications, and imaging.
Key features of the LTC2260IUJ-14 include an 800 MHz full-power bandwidth sample-and-hold, selectable input ranges from 1 V P-P to 2 V P-P, an optional data output randomizer to reduce switching spurs, an optional clock duty cycle stabilizer, plus shutdown and nap modes for power management. The serial SPI port allows configuration of output mode, input range, and power-down behavior without external hardware changes.
Architecture-wise, the part is pin-compatible with the 12-bit LTC2260-12 and with the higher/lower-speed LTC2261-14 (125 Msps) and LTC2259-14 (80 Msps) variants, simplifying platform design across resolutions. The ultralow 106 mW dissipation makes it useful for thermally constrained embedded systems and portable instruments.
Typical applications include communications baseband receivers, high-speed imaging and instrumentation, software-defined radios, portable test and measurement, and medical ultrasound front-end boards where 14-bit dynamic range and 105 Msps sample rate offer a strong speed/resolution/power balance.
When designing with this ADC, ensure the analog inputs are driven by a low-noise, low-distortion amplifier capable of settling within one aperture window, and keep the analog/digital ground returns separate to limit coupling. Decouple the analog supply with low-ESR ceramic capacitors close to the AVDD pins to preserve SFDR.
This page synthesizes distributor pricing, parametric drop-in alternatives within the same QFN-40 (6x6) family, and practical design notes that are not consolidated in the manufacturer datasheet alone.
ドロップイン代替品: LTC2260IUJ-14 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2260IUJ-14 （同一形状・フットプリント） — 相違点: Package, RoHS Status, Input Type, Power-Saving Modes, Sample Rate.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2260CUJ-14#PBF
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
LTC2261IUJ-14#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2259IUJ-14#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2258IUJ-14#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2260IUJ-14#TRPBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2260IUJ-14 最大定格＆電気的特性
| 分解能 | 14 bit |
| Sample Rate | 105 Msps |
| Number of Input Channels | 1 |
| Architecture | Pipelined |
| Supply Voltage (Analog/Digital) | 1.8 V (single supply) |
| Power Consumption | 106 mW at 105 Msps |
| INL (typical) | ±1 LSB |
| DNL (typical) | ±0.3 LSB |
| Transition Noise | 1.2 LSB RMS |
| Missing Codes | None over temperature |
| Input Range (selectable) | 1 V P-P to 2 V P-P |
| Full-Power Bandwidth | 800 MHz |
| Output Modes | CMOS, DDR CMOS, DDR LVDS |
| Output Supply Range | 1.2 V to 1.8 V (CMOS) |
| Configuration Interface | Serial SPI |
| Power-Saving Modes | Shutdown, Nap |
| Optional Features | Data output randomizer, clock duty cycle stabilizer |
| パッケージ | 40-QFN (6x6 mm) |
| Pin/Package Compatibility | Pin-compatible with LTC2260-12, LTC2261-14, LTC2259-14 |
| 動作温度範囲 | -40 C to +85 C (Industrial, IUJ suffix) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant (#PBF suffix) |
LTC2260IUJ-14 ピン構成
| ピン 1 | GND — Ground |
| ピン 2 | AIN+ — Differential analog input positive |
| ピン 3 | AIN- — Differential analog input negative |
| ピン 4 | VCM — Common-mode voltage output (approx mid-supply) |
| ピン 5 | GND — Ground |
| ピン 6 | REFH — Reference high decoupling node |
| ピン 7 | REFL — Reference low decoupling node |
| ピン 8 | GND — Ground |
| ピン 9 | AVDD — 1.8 V analog supply |
| ピン 10 | GND — Ground |
| ピン 11 | CLK+ — Differential clock input positive |
| ピン 12 | CLK- — Differential clock input negative |
| ピン 13 | OGND — Output driver ground |
| ピン 14 | OVDD — Output driver supply (1.2 V to 1.8 V) |
| ピン 15 | OE — Output enable (active high) / SDIO for SPI |
| ピン 16 | D0-/D0 — Data output bit 0 (DDR mode: negative edge) |
| ピン 17 | D0+/NC — Data output bit 0 positive edge (or NC depending on mode) |
| ピン 18 | D1-/D1 — Data output bit 1 |
| ピン 19 | D1+/NC — Data output bit 1 positive edge |
| ピン 20 | D2-/D2 — Data output bit 2 |
| ピン 21 | D2+/NC — Data output bit 2 positive edge |
| ピン 22 | D3-/D3 — Data output bit 3 |
| ピン 23 | D3+/NC — Data output bit 3 positive edge |
| ピン 24 | D4-/D4 — Data output bit 4 |
| ピン 25 | D4+/NC — Data output bit 4 positive edge |
| ピン 26 | D5-/D5 — Data output bit 5 |
| ピン 27 | D5+/NC — Data output bit 5 positive edge |
| ピン 28 | D6-/D6 — Data output bit 6 |
| ピン 29 | D6+/NC — Data output bit 6 positive edge |
| ピン 30 | D7-/D7 — Data output bit 7 |
| ピン 31 | D7+/NC — Data output bit 7 positive edge |
| ピン 32 | D8-/D8 — Data output bit 8 |
| ピン 33 | D8+/NC — Data output bit 8 positive edge |
| ピン 34 | D9-/D9 — Data output bit 9 |
| ピン 35 | D9+/NC — Data output bit 9 positive edge |
| ピン 36 | D10-/D10 — Data output bit 10 |
| ピン 37 | D10+/NC — Data output bit 10 positive edge |
| ピン 38 | D11-/D11 — Data output bit 11 |
| ピン 39 | D11+/NC — Data output bit 11 positive edge |
| ピン 40 | D12-/D12 — Data output bit 12 |
| ピン 41 | D12+/NC — Data output bit 12 positive edge |
| ピン 42 | D13-/D13 — Data output bit 13 |
| ピン 43 | D13+/NC — Data output bit 13 positive edge |
| ピン 44 | OF-/FRAME — Output flag / FRAME indicator |
| ピン 45 | CS — SPI chip select (active low) |
| ピン 46 | SCK — SPI serial clock |
| ピン 47 | SDO — SPI serial data output |
| ピン 48 | GND — Exposed pad ground (thermal pad on bottom of QFN) |
主な用途
LTC2260IUJ-14 の用途: 6 件s: Communications Baseband Receiver, Software-Defined Radio (SDR) Front End, Medical Ultrasound Beamformer, Portable Test & Measurement Instrumentation, High-Speed Imaging & Machine Vision, Industrial Data Acquisition Systems.
Communications Baseband Receiver
The LTC2260IUJ-14 fits baseband digitization of cellular and wireless infrastructure receivers where 14-bit resolution and 105 Msps sampling capture complex I/Q waveforms with adequate dynamic range. Its selectable DDR LVDS outputs and separate 1.2-1.8 V OVDD simplify interfacing to modern FPGAs such as Xilinx and Altera devices without external level translation, while the 106 mW dissipation supports dense multi-channel receiver cards.
おすすめ
Software-Defined Radio (SDR) Front End
The LTC2260IUJ-14's 800 MHz full-power analog bandwidth allows direct undersampling of IF frequencies well above the 52.5 MHz Nyquist limit, enabling wideband SDR capture with a single ADC channel. Its 1.2 LSB RMS transition noise preserves spurious-free dynamic range for narrowband signal extraction, while 106 mW dissipation is friendly to battery-powered SDR platforms and cognitive-radio prototypes.
おすすめ
Medical Ultrasound Beamformer
Ultrasound front-end boards require low-power, high-resolution ADCs to digitize echoes across many channels simultaneously. The LTC2260IUJ-14's 14-bit dynamic range and 106 mW dissipation per channel enable dense channel-count boards without aggressive thermal management, while the pin-compatible LTC2261-14 (125 Msps) and LTC2259-14 (80 Msps) allow tiered channel sampling rates within a single PCB platform.
おすすめ
Portable Test & Measurement Instrumentation
Handheld oscilloscopes, spectrum analyzers, and data-acquisition modules benefit from the LTC2260IUJ-14's 1.8 V single-supply operation and 106 mW dissipation, which together extend battery run-time while preserving 14-bit measurement accuracy. The optional clock duty-cycle stabilizer relaxes FPGA source-synchronous timing margins, allowing lower-cost clocking in field-deployed instruments.
おすすめ
High-Speed Imaging & Machine Vision
Line-scan and area-scan cameras requiring 14-bit pixel depth at high frame rates leverage the LTC2260IUJ-14's 105 Msps capability and DDR LVDS output for fast off-board transfer. The 800 MHz input bandwidth supports CCD/CIS analog front ends with minimal group-delay variation, while shutdown/nap modes reduce power when scan lines are idle, conserving overall system energy budget.
おすすめ
Industrial Data Acquisition Systems
Multi-channel vibration, sonar, and process-control data-acquisition cards benefit from the LTC2260IUJ-14's industrial -40 C to +85 C temperature rating and pin-compatible family, letting one PCB support 80/105/125 Msps configurations. The serial SPI port enables in-system gain and output-mode reconfiguration during factory calibration cycles without hardware changes.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2260IUJ-14 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2260CUJ-14#PBF | LTC2261IUJ-14#PBF | LTC2259IUJ-14#PBF | LTC2258IUJ-14#PBF |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Sample Rate | 105 Msps | 105 Msps | 125 Msps | 80 Msps | 65 Msps |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Temperature Grade | Industrial -40 C to +85 C | Commercial 0 C to +70 C | Industrial -40 C to +85 C | Industrial -40 C to +85 C | Industrial -40 C to +85 C |
| Output Modes | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS |
主な差別化要因
- Pin-compatible with 12-bit and 12/14-bit speed siblings （vs LTC2260IUJ-12 (12-bit))
- Ultralow 106 mW dissipation （vs LTC2261IUJ-14 (125 Msps))
- Selectable 1 V P-P / 2 V P-P input range via SPI （vs LTC2258IUJ-14 (65 Msps))
設計ノート
Decouple AVDD with at least 1 x 10 uF bulk + 1 x 0.1 uF X7R ceramic close to each AVDD pin; place OVDD decoupling (1.2-1.8 V) similarly. The 106 mW dissipation across multiple channels quickly accumulates, so plan copper pour under the exposed pad to keep junction temperature within the -40 C to +85 C industrial envelope. Estimated: with theta_JA ~28 C/W for the 6x6 QFN and 106 mW dissipation, junction rise ~3 C above ambient - well within limits but rises proportionally if multiple ADCs are stacked.
Keep analog input traces matched and length-balanced to preserve 800 MHz full-power bandwidth; use 100-ohm differential routing for AIN+/AIN- and CLK+/CLK-. Route digital outputs (DDR LVDS or CMOS) on an inner layer separated by a solid ground plane to limit digital-to-analog coupling. Place the reference decoupling caps (REFH/REFL) within 2 mm of the package to avoid reference-noise degradation of SFDR.
Do not float the OE/CS pin - tie CS low only after configuring output mode via SPI. Mismatched impedance at the analog input causes INL degradation at high input frequencies; verify transformer or amplifier source impedance matches the 1 V P-P / 2 V P-P setting. Driving the analog input outside 0 to AVDD range risks latch-up; clamp with protection diodes for hot-plug-capable front ends.
コンプライアンス情報
#PBF suffix denotes RoHS-compliant / lead-free. REACH SVHC, halogen-free, and conflict-minerals declarations must be obtained from Analog Devices' environmental portal. Part is not AEC-Q100 qualified (industrial, not automotive).
