LTC2261IUJ-14 vs LTC2261IUJ-12 比較
詳細な並列比較: LTC2261IUJ-14 メーカー: Analog Devices および LTC2261IUJ-12 メーカー: Analog Devices。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | LTC2261IUJ-14 | LTC2261IUJ-12 |
|---|---|---|
| ブランド | Analog Devices | Analog Devices |
| カテゴリ | ADC/DAC | ADC/DAC |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $26.80 | $11.78 |
| 分解能 | 14 bits | 12 bits |
| Sample Rate | 125 Msps | 125 Msps |
| Architecture | Pipelined | Pipelined |
| Number of Channels | 1 | 1 |
| Input Type | Differential (single-ended capable with biasing) | — |
| Analog Supply Voltage (AVDD) | 1.8 V | — |
| Output Supply Voltage (OVDD) | 1.2 V to 1.8 V | — |
| Integral Nonlinearity (INL) | ±1 LSB (typical) | — |
| Differential Nonlinearity (DNL) | ±0.3 LSB (typical) | — |
| Transition Noise | 1.2 LSB RMS | 0.3 LSB RMS |
| Signal-to-Noise Ratio (SNR) | 73.4 dB | — |
| Spurious-Free Dynamic Range (SFDR) | 85 dB | — |
| Missing Codes | None over temperature | None over temperature |
| Digital Output Modes | Full-rate CMOS, DDR CMOS, DDR LVDS | Full-rate CMOS, DDR CMOS, or DDR LVDS |
| 動作温度範囲 | -40 °C to +85 °C (I grade) | — |
| パッケージ | 40-pin QFN (6x6 mm) with exposed pad | 40-pin QFN (UJ) 6 mm × 6 mm with exposed pad |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | Compliant (PBF suffix) | Compliant |
| 電源電圧 | — | 1.8 V (single) |
| Power Dissipation | — | 124 mW at 125 Msps |
| INL (Typical) | — | ±0.3 LSB |
| DNL (Typical) | — | ±0.1 LSB |
| Analog Input Bandwidth | — | 800 MHz full-power |
| Input Range | — | 1 Vp-p to 2 Vp-p (selectable) |
| Output Supply (DRVDD) | — | 1.2 V to 1.8 V (separate from AVDD) |
| 動作温度 | — | -40 °C to +85 °C (Industrial, I-grade) |
| Configuration Interface | — | Serial SPI port |
| Power-Saving Modes | — | Shutdown and Nap modes |