LTC2261IUJ-12 - 12-Bit 125Msps 1.8V Ultra-Low Power ADC | ADI
部品番号: LTC2261IUJ-12 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.85 | $168.50 |
| 100 | $14.92 | $1,492.00 |
| 500 | $13.2 | $6,600.00 |
| 1,000 | $11.78 | $11,780.00 |
LTC2261IUJ-12 概要
What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC architecture that processes input samples through multiple cascaded low-resolution stages, each stage resolving a portion of the conversion before handing the residue to the next stage. Pipelined ADCs sit in the hierarchy: ADC -> data converter -> signal chain IC -> semiconductor. They dominate applications from 10 Msps to several hundred Msps where both speed and resolution matter, especially in communications, imaging, and instrumentation front-ends.
The LTC2261IUJ-12 features selectable input ranges from 1 Vp-p to 2 Vp-p, an 800 MHz full-power analog input bandwidth sample-and-hold, and an optional clock duty-cycle stabilizer for clean sampling with non-50% clock sources. The digital outputs can be configured as full-rate CMOS, double-data-rate (DDR) CMOS, or DDR LVDS, with a separate output supply pin allowing the CMOS swing to be programmed from 1.2 V to 1.8 V for direct interface to ASICs and FPGAs. A serial SPI port provides configuration of output mode, input range, and power-down options.
Typical applications include basestation receive signal paths, portable instrumentation, handheld test equipment, low-power medical imaging, software-defined radio, and general-purpose multi-channel data acquisition where thermal budget and PCB area are tight. Pin-compatible 14-bit (LTC2261-14) and lower-speed 12-bit family members (LTC2260-12 at 105 Msps, LTC2259-12 at 80 Msps) allow designers to scale resolution and sampling rate without changing the PCB footprint.
Design consideration: choose CMOS outputs for low-cost FPGA connections with 1.2 V–1.8 V swing, or switch to LVDS for noise-immune long-trace routing above 100 Msps. Decouple AVDD and DVDD independently with 0.1 µF + 10 µF ceramics placed within 3 mm of the supply pins. This page combines distributor pricing, drop-in pin-compatible alternatives, and practical layout notes not duplicated in the manufacturer datasheet.
ドロップイン代替品: LTC2261IUJ-12 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2261IUJ-12 （同一形状・フットプリント） — 相違点: Package, RoHS Status, Transition Noise, Resolution, Sample Rate.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2260IUJ-12
✅ ドロップイン✓ 在庫あり
$11.75 / 個
データシートを見る →LTC2259IUJ-12
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2261IUJ-14
✅ ドロップイン✓ 在庫あり
$26.8 / 個
データシートを見る →LTC2261CUJ-12#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2261IUJ-12 最大定格＆電気的特性
| 分解能 | 12 bits |
| Sample Rate | 125 Msps |
| Architecture | Pipelined |
| Number of Channels | 1 |
| 電源電圧 | 1.8 V (single) |
| Power Dissipation | 124 mW at 125 Msps |
| INL (Typical) | ±0.3 LSB |
| DNL (Typical) | ±0.1 LSB |
| Transition Noise | 0.3 LSB RMS |
| Missing Codes | None over temperature |
| Analog Input Bandwidth | 800 MHz full-power |
| Input Range | 1 Vp-p to 2 Vp-p (selectable) |
| Digital Output Modes | Full-rate CMOS, DDR CMOS, or DDR LVDS |
| Output Supply (DRVDD) | 1.2 V to 1.8 V (separate from AVDD) |
| パッケージ | 40-pin QFN (UJ) 6 mm × 6 mm with exposed pad |
| 動作温度 | -40 °C to +85 °C (Industrial, I-grade) |
| Configuration Interface | Serial SPI port |
| Power-Saving Modes | Shutdown and Nap modes |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
LTC2261IUJ-12 ピン構成
| ピン 1 | AVDD — Analog 1.8 V supply |
| ピン 2 | AGND — Analog ground |
| ピン 3 | AIN+ — Differential analog input positive |
| ピン 4 | AIN- — Differential analog input negative |
| ピン 5 | AGND — Analog ground |
| ピン 6 | AVDD — Analog 1.8 V supply |
| ピン 7 | REFT — Top reference decoupling |
| ピン 8 | REFB — Bottom reference decoupling |
| ピン 9 | AGND — Analog ground |
| ピン 10 | AVDD — Analog 1.8 V supply |
| ピン 11 | ENC+ — Encode clock input positive |
| ピン 12 | ENC- — Encode clock input negative |
| ピン 13 | CS — SPI chip select (active low) |
| ピン 14 | SCK — SPI serial clock |
| ピン 15 | SDI — SPI serial data input |
| ピン 16 | SDO — SPI serial data output |
| ピン 17 | OGND — Output driver ground |
| ピン 18 | DRVDD — Output driver supply 1.2 V-1.8 V |
| ピン 19 | OUT0 — Digital output bit 0 (LSB) |
| ピン 20 | OUT1 — Digital output bit 1 |
| ピン 21 | OUT2 — Digital output bit 2 |
| ピン 22 | OUT3 — Digital output bit 3 |
| ピン 23 | OUT4 — Digital output bit 4 |
| ピン 24 | OUT5 — Digital output bit 5 |
| ピン 25 | OGND — Output driver ground |
| ピン 26 | DRVDD — Output driver supply 1.2 V-1.8 V |
| ピン 27 | OUT6 — Digital output bit 6 |
| ピン 28 | OUT7 — Digital output bit 7 |
| ピン 29 | OUT8 — Digital output bit 8 |
| ピン 30 | OUT9 — Digital output bit 9 |
| ピン 31 | OUT10 — Digital output bit 10 |
| ピン 32 | OUT11 — Digital output bit 11 (MSB) |
| ピン 33 | OGND — Output driver ground |
| ピン 34 | DRVDD — Output driver supply 1.2 V-1.8 V |
| ピン 35 | NC — Not connected (per datasheet) |
| ピン 36 | MODE — Output mode select (CMOS / LVDS) |
| ピン 37 | SHDN — Shutdown (active low) |
| ピン 38 | NAP — Nap mode (active low) |
| ピン 39 | AGND — Analog ground |
| ピン 40 | AVDD — Analog 1.8 V supply |
主な用途
LTC2261IUJ-12 の用途: 6 件s: Wireless Baseband Receiver, Portable Test and Measurement, Software Defined Radio, Medical Ultrasound Receive Path, Industrial Multi-Channel Data Acquisition, Low-Power Imaging and Video Processing.
Wireless Baseband Receiver
The LTC2261IUJ-12's 125 Msps sampling rate and 800 MHz full-power analog input bandwidth make it well-suited for digitizing IF signals in 4G LTE and 5G NR small-cell base stations. Its 12-bit resolution captures the dynamic range needed for multi-carrier QAM demodulation while the 124 mW dissipation keeps the remote-radio-head thermal budget under control. The DDR LVDS output mode drives FPGAs across backplanes without level shifters. Place AVDD and DRVDD decoupling within 3 mm of the pins and route the LVDS pairs as 100 ohm differential microstrip.
おすすめ
Portable Test and Measurement
Handheld oscilloscopes and spectrum analyzers benefit from the LTC2261IUJ-12's 124 mW dissipation and 1.8 V single-supply operation, extending battery runtime in field-instrument designs. The 12-bit, 125 Msps performance captures waveforms to ~60 MHz analog bandwidth with 70 dB SNR, sufficient for general-purpose signal integrity debugging. The Nap and Shutdown modes drop consumption to microamp range between acquisition bursts. Designers can scale to the 14-bit LTC2261IUJ-14 on the same PCB for higher-end analyzers.
おすすめ
Software Defined Radio
The LTC2261IUJ-12 fits SDR receiver front-ends where 12-bit resolution and 125 Msps sampling digitize 0-60 MHz IF blocks at a low 124 mW power budget. Its selectable 1 Vp-p or 2 Vp-p input range supports direct connection to common LNA / mixer outputs, while DDR LVDS outputs feed gigabit-rate FPGA transceivers without parallel bus congestion. The integrated SPI port lets host processors reconfigure input range and output mode in the field, enabling multi-mode radio platforms on a single PCB.
おすすめ
Medical Ultrasound Receive Path
Portable ultrasound carts and handheld imaging probes benefit from the LTC2261IUJ-12's low 124 mW dissipation, 1.8 V single supply, and 800 MHz input bandwidth for digitizing multi-MHz piezo return signals. The 12-bit resolution captures diagnostic-grade echo amplitude, while the DDR LVDS option routes 12-bit data across flex cables to the beamformer FPGA without EMI. The 40-pin QFN (6x6) footprint packs dense channel arrays into compact probe heads. Designers scale to the 14-bit LTC2261IUJ-14 for premium cart systems.
おすすめ
Industrial Multi-Channel Data Acquisition
The LTC2261IUJ-12 supports simultaneous-sampling multi-channel DAQ modules where 125 Msps per channel is paired with a multiplexer front-end and FPGA post-processing. The 1.8 V single supply simplifies power tree design across 4/8/16 channel modules, while the optional data output randomizer reduces EMI in long cable runs to the controller. With 124 mW per channel and exposed-pad QFN package, designers stack multiple ADCs in tight thermal footprints. Use LVDS outputs above 100 Msps to maintain signal integrity.
おすすめ
Low-Power Imaging and Video Processing
The LTC2261IUJ-12 digitizes intermediate-frequency video signals in low-power broadcast, security camera, and machine-vision pipelines. Its 12-bit resolution captures HDR scene data, while 124 mW at 125 Msps fits fanless embedded designs. The selectable CMOS or LVDS output mode flexibly connects to ASICs, FPGAs, or DSP processors. The shutdown and Nap modes drop idle power for duty-cycled motion-triggered capture, extending battery life in remote camera deployments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2261IUJ-12 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2260IUJ-12 | LTC2259IUJ-12 | LTC2261IUJ-14 | LTC2261CUJ-12#PBF |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (6x6) UJ | 40-QFN (6x6) UJ - same | 40-QFN (6x6) UJ - same | 40-QFN (6x6) UJ - same | 40-QFN (6x6) UJ - same |
| Resolution | 12 bits | 12 bits | 12 bits | 14 bits | 12 bits |
| Sample Rate | 125 Msps | 105 Msps | 80 Msps | 125 Msps | 125 Msps |
| Supply Voltage | 1.8 V single | 1.8 V single | 1.8 V single | 1.8 V single | 1.8 V single |
| Temperature Grade | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C | Commercial 0C to +70C |
| Output Modes | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS |
主な差別化要因
- Highest sample rate in the 12-bit / 40-QFN pin-compatible LTC2261 family （vs LTC2260IUJ-12)
- 12-bit density optimized for low-power signal chains （vs LTC2261IUJ-14)
- Industrial temperature grade variant of the same die （vs LTC2261CUJ-12#PBF)
設計ノート
Place AVDD and DRVDD decoupling capacitors within 3 mm of the supply pins: a 0.1 µF X7R ceramic in parallel with a 10 µF X5R ceramic per pin is recommended per the 226112fc reference schematic. Keep analog and digital ground returns separated and join them only at the exposed pad beneath the QFN. Route the ENC+/ENC- differential clock as a 100 ohm matched pair and keep it isolated from analog input traces to avoid coupled clock noise on the input.
When using DDR LVDS output mode, route each LVDS pair as a length-matched 100 ohm differential microstrip with 2W trace spacing. Place the receiver-side 100 ohm termination as close as possible to the FPGA pins. Maintain a continuous ground reference plane beneath the LVDS pairs and avoid routing across split planes; this keeps the eye diagram clean at 125 Msps. For CMOS output above 80 Msps, consider series damping resistors to control edge rates.
Avoid driving the AIN+/AIN- pins with single-ended signals when input range is set to 2 Vp-p - this halves the available SNR and may violate the common-mode input range. Always drive the ADC differentially through a low-noise ADC driver such as the AD8475 or AD8021. The clock duty-cycle stabilizer must be enabled when the ENC source is not 50% duty cycle, otherwise aperture jitter degrades SNR. Finally, do not exceed 1.98 V on AVDD; the absolute maximum is 2 V per the 226112fc absolute ratings table.
Use a low-noise LDO such as ADP150 for the AVDD rail and a separate LDO for DRVDD to prevent digital switching noise from coupling into the analog supply. Add a ferrite bead in series with DRVDD if the FPGA or ASIC load creates large transient currents. The shutdown pin should be tied high through a 100 kohm resistor when shutdown control is not used to prevent floating-state leakage.
コンプライアンス情報
Pb-free per #PBF / #TRPBF suffix. RoHS compliant per ADI product page. Not AEC-Q100 qualified; for automotive applications, contact ADI about AEC-Q100 grade variants. Halogen-free status not explicitly stated in provided data.
